Semiconductor Device Ineffective Region Yield

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The development of semiconductor devices for power electronics is hindered by large-area semiconductor chips that often contain defects, leading to reduced yield, with existing technologies failing to effectively address process-related defects such as sticking particles and pattern defects in addition to crystalline defects.

Innovation Solution

A semiconductor device and manufacturing method that involves a semiconductor substrate with well regions and a drift region, where a gate insulating layer exposes source regions both inside and outside an ineffective region, and a gate electrode is only disposed outside this region, with an insulating film covering the gate electrode and part of the gate insulating layer inside the ineffective region, and a source wire is formed to contact the exposed source regions through source contact holes both inside and outside the ineffective region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If large-area semiconductor chips are used for power electronics applications, then the current handling capability is improved, but the yield is reduced due to the presence of defects

Engineering Contradiction:
Improvecurrent handling capabilityVSAvoidyield
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The semiconductor chip surface is divided into effective regions and ineffective regions. The ineffective regions contain defects but are excluded from active device operation, while effective regions maintain full functionality. This segmentation allows large-area chips to be used without allowing defects to degrade overall yield.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Defective areas are extracted and isolated as ineffective regions through the formation of gate insulating layers and insulating films that prevent these regions from participating in device operation. This extraction removes the harmful effect of defects while preserving the functional areas.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If traditional defect prevention technologies are applied, then some defects are prevented, but process-related defects such as sticking particles and pattern defects are not effectively addressed

Engineering Contradiction:
Improvedefect preventionVSAvoidcoverage of defect types
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

Gate insulating layers and insulating films are formed in advance during the manufacturing process to define ineffective regions. This preliminary action ensures that even process-related defects occurring later will not affect device functionality, as the protective structure is already in place.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Areas containing process-related defects (sticking particles, pattern defects) are converted into ineffective regions that are electrically isolated. The presence of these defects no longer harms device performance because they are confined to regions that do not participate in active operation.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Device complexity

If the gate electrode is disposed over the entire gate insulating layer, then the device structure is simplified, but defects in any region can cause yield reduction

Engineering Contradiction:
Improvegate electrode structureVSAvoidyield
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The gate electrode structure is made non-uniform by excluding it from ineffective regions while maintaining it in effective regions. This local differentiation ensures that defects in ineffective regions cannot cause yield reduction, while the simplified structure is maintained in functional areas.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10262909B2Semiconductor device and method for manufacturing the same
Publication Date: 2019.04.16 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD
  • US10262909B2 patent drawing
  • US10262909B2 patent drawing
  • US10262909B2 patent drawing

AI summary

Semiconductor layer is formed on semiconductor substrate. Semiconductor layer has a plurality of well regions in a surface remote from semiconductor substrate. Semiconductor layer includes drift region in addition to the plurality of well regions. The plurality of well regions each include body region, source region, and contact region. Source region is in contact with body region. Contact region is in contact with both body region and source region. Body region, source region, and source wire are at an identical potential because of contact region. Semiconductor layer includes ineffective region R at the surface remote from semiconductor substrate.