Semiconductor Structure With Inner Interconnect for Lower Resistance
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Solution Overview
Problem
The increasing complexity of manufacturing semiconductor devices at a miniaturized scale leads to issues such as high yield loss, reduced reliability of electrical interconnections, and low testing coverage, necessitating improvements in device robustness, manufacturing cost, and processing time.
Innovation Solution
The introduction of an inner interconnect structure (IIS) within the semiconductor device, which provides a shorter conduction path and additional connection opportunities between source/drain regions of upper and lower FETs, thereby enhancing device performance and reducing electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional manufacturing methods are used for miniaturized semiconductor devices, then device geometric size decreases, but manufacturing complexity increases and yield loss increases
Solution Approach 1:
The patent segments the interconnection structure into multiple layers including upper and lower interconnect layers with through-substrate vias. This segmentation allows each layer to be optimized independently for miniaturization while maintaining overall system functionality, thereby reducing manufacturing complexity despite smaller device dimensions
Solution Approach 2:
The patent introduces a vertical dimension with through-substrate vias connecting upper and lower interconnect layers. This three-dimensional interconnection approach enables shorter signal paths and reduced parasitic effects compared to planar interconnections, addressing manufacturing challenges in miniaturized devices by utilizing the vertical space
2Productivity
If device size is reduced, then functional density increases, but electrical interconnection reliability decreases
Solution Approach 1:
The patent employs vertical through-substrate vias to create three-dimensional interconnections, which provide shorter and more direct electrical paths compared to traditional planar routing. This reduces the number of interconnection steps and potential failure points, thereby improving reliability while enabling higher functional density in miniaturized devices
Solution Approach 2:
The patent introduces intermediate buffer layers and insulation layers between conductive elements. These intermediary structures provide electrical isolation and mechanical support, ensuring stable and reliable electrical connections as devices are scaled down to smaller dimensions where parasitic effects become more significant
3Loss of time
If manufacturing process is simplified, then processing time decreases, but device robustness may be compromised
Solution Approach 1:
The patent incorporates preliminary formation of via holes and insulation layers during earlier fabrication stages. By preparing the interconnection structure in advance, subsequent processing steps are simplified and can be performed more quickly, reducing overall processing time while maintaining device robustness through proper structural preparation
Solution Approach 2:
The patent combines multiple functions into integrated structures, such as forming insulation layers that simultaneously provide electrical isolation and mechanical support. This merging of functions reduces the number of separate processing steps required, decreasing processing time while maintaining device robustness through multi-functional structural elements
Data Source
AI summary
A semiconductor device includes a first transistor and a second transistor. The first transistor is of a first type in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is of a second type arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device further includes a first conductive line in a third layer between the first and second layers. The first conductive line electrically connects a first source/drain region of the first active region to a second source/drain region of the second active region. The gate comprises an intermediate portion disposed between the first active region and the second active region, wherein the first conductive line crosses the gate at the intermediate portion.