Semiconductor Inner Interconnection Structure for TSV Placement
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Solution Overview
Problem
The arrangement of solder balls on semiconductor chips is restricted by JEDEC standards, which limits the placement of Through Silicon Via (TSV) structures and increases the electrical signal path, necessitating additional substrates for connection routing.
Innovation Solution
A semiconductor device with an inner interconnection structure featuring vertical connection vias and horizontal buried conductive lines that allow for flexible connection of first and second connection terminals, eliminating the need for external substrates by using dielectric vias to separate conductive lines and reduce signal paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder balls are arranged according to JEDEC standards for external connection terminals, then the arrangement follows industry standards and ensures compatibility, but the TSV placement is restricted and the electrical signal path is increased
Solution Approach 1:
The patent introduces horizontal buried conductive lines that extend in the planar dimension rather than relying solely on vertical TSV connections. This allows connection terminals to be connected through a combination of horizontal buried lines and vertical vias, enabling TSV placement flexibility while maintaining solder ball arrangement compatibility
Solution Approach 2:
The patent introduces an inner interconnection structure consisting of buried conductive lines as intermediary elements between solder balls and TSVs. These buried lines act as mediators that can route signals horizontally within the substrate, decoupling the placement locations of solder balls from TSV positions and reducing the need for lengthy external signal paths
2Reliability
If TSV is located in restricted regions (edge or center regions with scribe lane) to avoid active regions, then circuit elements are protected, but the exposure location of TSV is restricted and requires additional substrates for connection routing
Solution Approach 1:
The patent utilizes the horizontal dimension within the substrate by introducing buried conductive lines that can extend laterally to connect TSVs located in restricted regions to appropriate connection terminals. This internal horizontal routing eliminates the need for external PCB routing, simplifying the overall device structure while protecting circuit elements
Solution Approach 2:
The patent merges the functions of external connection terminals and internal signal routing by integrating buried conductive lines directly into the substrate. This combines the TSV connection function with the signal routing function, eliminating the need for separate external substrates and reducing device complexity
3Adaptability or versatility
If PCB or rearrangement interconnection is disposed between solder ball and semiconductor chip to electrically connect them, then connection flexibility is improved, but the electrical signal path is increased and device complexity is increased
Solution Approach 1:
The patent extracts the signal routing function from external substrates and relocates it internally within the semiconductor chip through buried conductive lines. This eliminates the need for external PCB or rearrangement interconnection structures, shortening the electrical signal path while maintaining connection flexibility through the internal buried line network
Solution Approach 2:
The patent merges the connection terminal function with the signal routing function by integrating buried conductive lines that directly connect solder balls to TSVs within the substrate. This consolidation eliminates external connection structures, reducing signal path length and improving transmission speed while maintaining adaptability
Data Source
AI summary
A semiconductor device includes a semiconductor chip and an inner interconnection structure. The semiconductor chip includes a front surface that exposes first connection terminals and a rear surface that is opposite to the front surface and exposes second connection terminals separated from the first connection terminals. The inner interconnection structure includes horizontal buried conductive lines and vertical connection lines disposed to pierce the semiconductor chip to connect the first connection terminals and the second connection terminals.