Semiconductor Inner Spacers with Graded Dimensions for Nanosheet Integration
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Solution Overview
Problem
The increasing demands for high performance and integration in semiconductor devices require fine-patterned structures, such as FinFETs and nanosheet transistors, which face challenges in maintaining operating characteristics due to size reduction and spacing limitations.
Innovation Solution
A semiconductor device design featuring a gate structure with varying inner spacers of different heights and thicknesses, where the spacers' thickness decreases towards the bottom, and a source/drain region with epitaxial layers of varying doping concentrations, enhancing stability and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased to meet high performance demands, then the device can achieve higher performance and speed, but the spacing distance between patterns becomes finer and more difficult to manufacture
Solution Approach 1:
The gate structure is divided into multiple segments along the channel direction, with each segment having independently controllable inner spacers. This segmentation allows for optimized spacing control in different regions, enabling finer pattern integration while maintaining manufacturable spacing through localized spacer thickness adjustment.
Solution Approach 2:
The inner spacers are designed with non-uniform thickness along the channel direction, with thinner spacers in regions requiring finer spacing and thicker spacers where larger spacing is needed. This local quality variation enables the device to achieve high integration density in critical areas while maintaining manufacturing precision where spacing constraints are less stringent.
2Productivity
If the pattern width is reduced to achieve fine-patterned structures, then the device can achieve higher integration, but the operating characteristics deteriorate due to size reduction
Solution Approach 1:
The inner spacers provide localized structural support and electrical isolation at critical regions where pattern width is reduced. By positioning spacers with optimized thickness at specific locations along the channel, the design maintains adequate spacing to prevent short circuits and maintain electrical characteristics even when overall pattern dimensions are scaled down for higher integration.
Solution Approach 2:
The inner spacers act as intermediary structures between adjacent patterned regions, providing physical separation and electrical isolation. This intermediary element enables the device to achieve finer pattern widths while maintaining reliable operating characteristics through the spacer-mediated control of inter-pattern spacing and electrical fields.
3Productivity
If the spacing distance is reduced to increase integration, then more devices can be packed, but the manufacturing precision requirements increase
Solution Approach 1:
The inner spacers are formed as preliminary structures during the fabrication process, establishing the spacing between patterned regions before final patterning steps. By pre-defining spacer thickness and position, the design enables subsequent fine-pattern formation with controlled spacing, reducing the manufacturing precision burden on later high-resolution patterning steps.
Solution Approach 2:
The spacer thickness is varied as a controllable parameter along the channel direction, with thickness values optimized for different spacing requirements. This parameter change enables the device to achieve reduced spacing distances in integration-critical regions while maintaining manufacturable spacing tolerances in other regions, effectively decoupling integration density from uniform high-precision spacing requirements.
Data Source
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Figure 3A
AI summary
A semiconductor device includes: a gate structure (160) having a side in a first direction (X) and extending in a second direction (Y) intersecting the first direction (X); a source/drain (130) region on the side of the gate structure (160); a plurality of channel layers (141, 142, 143) spaced apart from each other in a third direction (Z) intersecting the first direction (X) and the second direction (Y) and surrounded by the gate structure (160); and a plurality of inner spacers between the gate structure (160) and the source/drain region (130), wherein the plurality of inner spacers have respective heights in the third direction (Z) increasing in the third direction (Z) toward bottom, and have respective thicknesses in the first direction (X) decreasing in the third direction (Z) toward bottom.