Semiconductor Insertion Pattern for HEIP Control
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Solution Overview
Problem
The increased integration in semiconductor devices leads to deterioration in Hot Electron Induced Punch-through (HEIP) characteristics for p-MOS transistors of DRAM devices, and existing solutions that expand the gate electrode compromise reliability and operation speed.
Innovation Solution
A semiconductor device design that includes a field pattern with an insulating region on a nitride liner in a trench adjacent to an active region, featuring an elongate conductive insertion pattern without a nitride liner between its sidewalls and the field pattern, which improves the HEIP characteristics without expanding the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the gate electrode is expanded adjacent to the field region to address HEIP characteristics, then HEIP characteristics improve, but reliability and operation speed deteriorate
Solution Approach 1:
The gate electrode structure is segmented into a main gate electrode and a separate insertion pattern (conductive region). The insertion pattern is positioned in the peripheral region adjacent to the field region, while the main gate electrode remains in the cell region. This segmentation allows the insertion pattern to address HEIP characteristics without requiring expansion of the main gate electrode, thereby maintaining reliability and operation speed.
Solution Approach 2:
The insertion pattern acts as an intermediary conductive structure between the gate electrode and the field region. It provides the necessary electrical field control to mitigate HEIP effects without directly expanding the gate electrode structure. The insertion pattern is electrically connected to the gate electrode through conductive connections, serving as a mediator that achieves HEIP control while preserving the original gate electrode dimensions and device performance characteristics.
2Object-affected harmful factors
If the gate electrode is expanded adjacent to the field region, then HEIP characteristics improve, but operation speed deteriorates
Solution Approach 1:
The gate control function is segmented between the main gate electrode (in cell region) and the insertion pattern (in peripheral region). This allows the insertion pattern to provide localized field control for HEIP mitigation without increasing the overall gate electrode area that would slow down device operation. The segmented structure enables independent optimization of HEIP control and operation speed.
Solution Approach 2:
The insertion pattern provides localized field control specifically in the peripheral region where HEIP effects occur, without expanding the gate electrode in the cell region where fast operation is critical. This local quality approach allows HEIP mitigation to be applied only where needed, preserving the fast operation characteristics of the main transistor structure.
3Productivity
If integration is increased, then device density improves, but HEIP characteristics deteriorate
Solution Approach 1:
The HEIP control function is extracted from the main gate electrode structure and implemented as a separate insertion pattern in the peripheral region. This extraction allows high integration in the cell region to be maintained while adding dedicated HEIP control capability in the peripheral region. The separation enables independent optimization of integration density and HEIP characteristics without compromise.
Solution Approach 2:
The solution moves from a two-dimensional planar expansion of the gate electrode to a three-dimensional structure with the insertion pattern positioned in the peripheral region. This dimensional change allows HEIP control to be achieved through vertical and lateral positioning of the insertion pattern rather than through horizontal expansion of the gate electrode, enabling high integration while maintaining good HEIP characteristics.
Data Source
AI summary
A semiconductor device includes a substrate including a memory cell region and a peripheral region and a field pattern including an insulating region disposed on a nitride liner in a trench in the substrate adjacent an active region. The field pattern and the active region extend in parallel through the cell and peripheral regions. The device also includes a transistor in the peripheral region including a source/drain region in the active region. The device further includes an insertion pattern including an elongate conductive region disposed in the substrate and extending along a boundary between the field pattern and the active region in the peripheral region. Fabrication methods are also described.