Semiconductor Inspection Apparatus for Reticle Error Correction
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Solution Overview
Problem
In semiconductor manufacturing, split exposure techniques face challenges in achieving high precision alignment due to differences in rendering errors among reticles, leading to deviations in partial patterns within the same layer, which existing methods fail to accurately manage and correct.
Innovation Solution
An inspection apparatus and manufacturing method that utilize a combination of exposure shots and inspection marks to derive and correct linear components of errors caused by reticles and wafer positions, enabling precise connection of partial patterns even when using reticles with different rendering errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If split exposure is used to manufacture semiconductor devices with large chip size and fine patterns, then the exposure range is extended to accommodate large chips, but positioning precision and alignment accuracy deteriorate due to rendering errors among reticles and wafer position variations
Solution Approach 1:
The patent applies preliminary action by measuring and deriving linear error components (magnification, rotation, translation) from inspection marks before performing split exposure and single-batch exposure. These error components are calculated in advance and used to correct positioning deviations, ensuring high-precision alignment across multiple exposure shots without requiring real-time adjustment during the exposure process.
Solution Approach 2:
The patent implements feedback by measuring the actual positions of inspection marks formed by different exposure shots, deriving error components from these measurements, and using the derived errors to correct positioning for subsequent exposure shots. This closed-loop feedback mechanism continuously refines alignment accuracy despite variations in reticle rendering errors and wafer position.
2Area of stationary object
If multiple reticles are used for split exposure, then the complexity of the exposure process increases to manage different partial patterns, but the ability to manufacture large chip devices is improved
Solution Approach 1:
The patent applies universality by creating a unified error correction framework that works across all exposure shots regardless of whether they are performed by split exposure or single-batch exposure. The same inspection mark measurement and error derivation process is universally applied to all reticles and exposure shots, simplifying the management of multiple reticles while enabling large chip manufacturing.
3Manufacturing precision
If inspection marks are used to measure positioning accuracy, then alignment precision is improved, but the complexity of measurement and error derivation increases
Solution Approach 1:
The patent extracts only the linear components (magnification, rotation, translation) of positioning errors from the inspection mark measurements, separating these critical error components from other potential error sources. This extraction approach focuses measurement complexity only on the essential linear error parameters that affect alignment precision, rather than attempting to measure and correct all possible error types.
Data Source
AI summary
An inspection apparatus inspecting a wafer on which a plurality of patterns are formed by a plurality of exposure shots, the inspection apparatus comprising: acquisition unit configured to acquire first information representing a positional relation between an inspection mark included in a pattern formed by a first exposure shot and an inspection mark included in a pattern formed by a second exposure shot, and second information representing a positional relation between the inspection mark included in the pattern formed by the second exposure shot and an inspection mark included in a pattern formed by a third exposure shot; and derivation unit configured to derive a linear component of an error caused by a reticle, and a linear component of an error caused by a position of a wafer, on the basis of the first information and the second information.