Semiconductor Insulating Layer Height Management for DRAM Filling
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Solution Overview
Problem
The miniaturization of DRAM devices leads to reduced cell area, making it difficult to maintain sufficient capacitance and signal-to-noise ratio, and the integration of memory cells causes overlay margin issues between contact plugs, affecting DRAM performance and process yield.
Innovation Solution
A semiconductor device structure with a periphery gate stacking structure and a cell stacking structure where the first insulating layer is formed higher than the substrate, allowing for improved filling and reducing the need for re-forming the gate oxide layer in the periphery region, thus avoiding damage to bit lines during high-temperature processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the cell area is reduced to increase memory cell integration, then the number of memory cells per device increases, but the capacitance and signal-to-noise ratio decrease
Solution Approach 1:
The patent transitions from planar capacitor structures to vertically stacked capacitor structures. The storage capacitor is formed by stacking multiple insulating layers and conductive layers vertically over the transistor, extending in the third dimension (vertical direction). This dimensional change allows the capacitor to maintain sufficient capacitance in reduced cell areas by increasing the effective capacitor area through vertical stacking rather than lateral expansion.
2Manufacturing precision
If the gate oxide layer is formed in the periphery region after bit lines are formed, then the gate oxide layer can be formed uniformly, but the bit lines are destroyed by high temperature during the gate oxide formation process
Solution Approach 1:
The patent performs the gate oxide layer formation process in the periphery region before forming the bit lines. By executing the high-temperature gate oxide formation process earlier in the manufacturing sequence, the bit lines are not yet present to be damaged by the high temperature. This preliminary action sequence prevents the destruction of bit lines while still achieving uniform gate oxide layer formation.
Data Source
AI summary
The present invention provides a semiconductor structure including a substrate defining a memory cell region and a peripheral region, a periphery gate stacking structure located within the peripheral region, wherein the periphery gate stacking structure includes at least a first gate layer, and a second gate layer disposed on the first gate layer. The semiconductor structure further includes a cell stacking structure located within the memory cell region, the cell stacking structure having at least a first insulating layer partially disposed in the substrate, a top surface of the first insulating layer being higher than a top surface of the substrate, and the top surface of the first insulating layer and a top surface of the first gate layer being on a same level.