Semiconductor Insulating Layer Thickness for EMI and Chipping
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Solution Overview
Problem
Conventional semiconductor devices face challenges in suppressing electromagnetic interference between secondary wires and electronic circuits, leading to signal delays and increased parasitic capacitance, while also experiencing issues with wafer curvature and chipping during the dicing process due to complex structures and insulating layer thickness variations.
Innovation Solution
A semiconductor device design featuring a semiconductor chip with a lower insulating layer exposing electrode pads, a secondary wire with pad, land, and wiring sections, and an upper insulating layer, where the insulating layers are thinner in secondary-wire-free areas and thicker in secondary-wire-containing areas, made of organic material with a larger coefficient of linear expansion to minimize electromagnetic interference and wafer curvature, and strategically omitting insulating layers near the edge to reduce chipping risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If secondary wires are arranged to avoid overlapping electronic circuits, then electromagnetic interference is suppressed, but wire length increases causing signal delays
Solution Approach 1:
The patent divides the insulating layer into multiple segments with different thicknesses: a first insulating layer beneath the secondary wire and a second insulating layer in areas without secondary wires. This segmentation allows the secondary wire to overlap the electronic circuit while the thicker first insulating layer suppresses electromagnetic interference, and the thinner second insulating layer reduces overall wire length requirements.
Solution Approach 2:
The patent applies different insulating layer thicknesses in different locations: a greater thickness in the secondary-wire-containing area to suppress electromagnetic interference, and a lesser thickness in the secondary-wire-free area to reduce overall complexity and wire length. This local differentiation resolves the contradiction between interference suppression and signal delay.
2Object-affected harmful factors
If secondary wires are routed around the periphery of electrode pads, then electromagnetic interference is reduced, but wire density increases causing manufacturing difficulties
Solution Approach 1:
The patent transitions from a two-dimensional planar routing approach to a three-dimensional solution by varying the insulating layer thickness in the vertical dimension. This allows secondary wires to be positioned more directly over electrode pads without increasing wire density, as the electromagnetic interference is suppressed by the thicker insulating layer rather than by spatial separation.
3Object-affected harmful factors
If insulating layers are made uniformly thick across the entire semiconductor chip, then electromagnetic interference is suppressed, but wafer curvature increases causing chipping during dicing
Solution Approach 1:
The patent applies different insulating layer thicknesses in different locations: a greater thickness in the secondary-wire-containing area to suppress electromagnetic interference, and a lesser thickness in the secondary-wire-free area to reduce wafer curvature and improve dicing reliability. This local differentiation resolves the contradiction between interference suppression and chipping resistance.
Solution Approach 2:
The patent utilizes the coefficient of linear expansion of organic insulating materials to manage wafer curvature. By reducing insulating layer thickness in areas without secondary wires, the overall stress and curvature of the wafer is reduced, preventing chipping during the dicing process while maintaining adequate thickness where needed for electromagnetic interference suppression.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses electromagnetic interference, reduces wafer curvature, and minimizes the risk of chipping during the dicing process by optimizing insulating layer thickness and structure, thereby maintaining electrical characteristics and manufacturing simplicity.
Implementation Method 1
made of organic material with a larger coefficient of linear expansion to minimize electromagnetic interference and wafer curvature
Implementation Method 2
the parasitic capacitance of an insulating layer existing between the secondary wires increases. This may cause wiring delays
Data Source
AI summary
A semiconductor device has a semiconductor chip provided with an insulating layer formed so as to be thinner in a first secondary-wire-free area than in a first secondary-wire-containing area. Further, the semiconductor chip has an edge extending further outward than a side wall, which severs as an edge of an upper insulating layer, in an extending direction of a circuit-forming surface of the semiconductor chip on which electrode pads are provided. This makes it possible to provide a semiconductor device capable of suppressing electromagnetic interference between a secondary wire and an electronic circuit of a semiconductor chip and the curvature of a wafer even in the case of overlap between the secondary wire and the electronic circuit, and of reducing the risk of occurrence of chipping in a dicing step.