Semiconductor Package Insulating Layout for Thermal Warpage Control
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Solution Overview
Problem
Semiconductor packages face a warping effect due to differences in the coefficients of thermal expansion among heterogeneous materials used in the package substrate, which can lead to reduced reliability.
Innovation Solution
The semiconductor package incorporates a package substrate with a patterned region, non-patterned region, and insulating regions, where the ratio of copper in the wiring layers varies between upper and lower regions, and insulating members are strategically placed to manage thermal expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If heterogeneous materials are stacked onto a single substrate to achieve miniaturization and weight reduction, then miniaturization and weight reduction are achieved, but warping effect occurs due to differences in coefficients of thermal expansion
Solution Approach 1:
The patent applies local quality by varying the copper ratio in wiring layers at different locations of the package substrate. Specifically, the copper ratio is adjusted in upper regions versus lower regions, and in central areas versus peripheral areas, to locally compensate for thermal expansion differences caused by heterogeneous material stacking. This spatial variation in material composition addresses the warping issue while maintaining the miniaturized heterogeneous structure.
2Volume of moving object
If heterogeneous materials are stacked onto a single substrate to achieve miniaturization, then miniaturization is achieved, but warping effect occurs due to differences in coefficients of thermal expansion
Solution Approach 1:
The patent implements local quality by strategically varying the copper ratio in wiring layers across different regions of the compact package substrate. The copper concentration is adjusted in upper versus lower regions and central versus peripheral areas, creating local compensatory effects that counteract thermal expansion-induced warping while maintaining the miniaturized three-dimensional heterogeneous structure.
3Stability of the object's composition
If the ratio of copper in wiring layers is varied between upper and lower regions, then warpage phenomenon is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies parameter changes by systematically varying the copper ratio parameter in wiring layers across different regions of the package substrate. This controlled parameter variation optimizes thermal expansion compensation to reduce warpage while maintaining compatibility with standard PCB manufacturing processes, thus balancing performance improvement with manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the warpage phenomenon in the semiconductor package, thereby enhancing its reliability and performance.
Implementation Method 1
differences in the coefficients of thermal expansion among these varied materials
Data Source
AI summary
According to an example embodiment, provided is a semiconductor package, including: a package substrate including a plurality of wiring layers and a plurality of insulating layers covering a portion of the plurality of wiring layers and a semiconductor chip mounted on the package substrate. At least a first insulating layer, among the plurality of insulating layers, comprises a first insulating member filling first and second regions and wherein a second insulating member filling a third region. The first region has a first wiring layer, among the plurality of wiring layers, and has first sides corresponding to edges of the package substrate and second sides between the first sides corresponding to corners of the package substrate. The second region is disposed between the first sides of the first region and the edges of the package substrate. The third region is disposed between the second sides of the first region and the corners of the package substrate.