Semiconductor Device Insulating Liners Spacers Blocking Layers
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Solution Overview
Problem
Highly integrated semiconductor devices face challenges with short circuits and deteriorated operating speed due to reduced distances between conductive lines and contact patterns, leading to poor device characteristics such as slower refreshing characteristics.
Innovation Solution
A semiconductor device design featuring a substrate with active regions, conductive lines, insulating liners, spacers, and blocking layers to maintain distance and prevent short circuits, while improving contact resistance and refreshing characteristics through specific layer configurations and manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between conductive lines and contact patterns is reduced to achieve higher integration, then device integration density is improved, but short circuit risk increases and device characteristics deteriorate
Solution Approach 1:
The patent introduces multiple intermediary structures between the conductive line and contact pattern: insulating liners are formed on the lower portion of the conductive line sidewalls, spacers are formed on the upper portion sidewalls, and blocking layers are positioned in recess portions. These intermediary structures physically separate the conductive line from the contact pattern, preventing direct contact and short circuits while allowing the structures to be positioned closer together for higher integration density.
Solution Approach 2:
The patent transitions from planar separation to three-dimensional separation by forming insulating liners and spacers on the sidewalls of the conductive line. This vertical/dimensional approach allows horizontal spacing to be reduced while maintaining isolation through vertical barrier structures, enabling higher integration without increasing short circuit risk.
2Productivity
If the distance between conductive lines and contact patterns is reduced, then integration density is improved, but capacitance increases causing slower operating speed
Solution Approach 1:
The insulating liners, spacers, and blocking layers act as dielectric intermediaries between the conductive line and contact pattern. These layers increase the effective insulation distance and reduce parasitic capacitance between adjacent structures, allowing closer spacing without degrading signal speed or refreshing characteristics.
Solution Approach 2:
The patent uses composite insulating structures combining multiple materials with different properties: insulating liners provide base isolation, spacers provide additional spacing control, and blocking layers provide localized capacitance reduction. This composite approach optimizes both integration density and electrical performance.
3Reliability
If multiple insulating structures (liners, spacers, blocking layers) are added to prevent short circuits, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the insulating function into distinct components: insulating liners on the lower portion, spacers on the upper portion, and blocking layers in recess portions. Each segment addresses specific isolation needs at different locations, providing reliable short circuit prevention while allowing targeted optimization of each structure's formation process.
Solution Approach 2:
The insulating liners are formed preliminarily on the conductive line sidewalls before spacer formation. This preliminary action establishes a foundation for subsequent spacer deposition and positioning, enabling a systematic multi-step process that builds complexity in a controlled sequence rather than attempting to form all structures simultaneously.
Data Source
AI summary
A semiconductor device includes: a substrate having active regions defined by a device isolation region; a conductive line extending in a direction on the active regions; insulating liners on both sidewalls of a lower portion of the conductive line that contacts with the active regions; spacers that are apart from the insulating liners in a direction perpendicular to a surface of the substrate and sequentially formed on both sidewalls of an upper portion of the conductive line; a blocking layer arranged at a spacing between a spacer located in the middle of the spacers and the insulating liners and in a recess portion recessed from one end of the spacer located in the middle of the spacers toward the conductive line; and conductive patterns arranged on the active regions on both sides of the spacers.