Insulating Structure for Semiconductor Module Isolation
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Solution Overview
Problem
Integrated semiconductor devices, particularly in automotive applications, face reliability issues due to electrostatic discharge (ESD) pulses and energetic electric pulses that can induce noise and malfunction by causing substrate potential fluctuations, affecting the operation of digital and analog modules.
Innovation Solution
The implementation of a lateral power integrated circuit design with a semiconductor body featuring a first and second well of different conductivity types, a silicon layer, and an insulating region to decouple and insulate modules, using a non-monocrystalline semiconductor layer and a vertical trench to prevent cross-talk and absorb pulses within individual modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If modules are integrated on a common substrate to minimize cost, size and weight, then integration density improves, but substrate potential fluctuations increase due to ESD pulses and energetic electric pulses
Solution Approach 1:
The patent divides the common substrate into multiple isolated potential wells (first potential well for digital circuits, second potential well for analog circuits, third potential well for power circuits) separated by insulating structures. This segmentation prevents ESD pulses and energetic electric pulses from causing substrate potential fluctuations that would affect other modules, while maintaining integration on a single substrate to minimize device size.
2Reliability
If insulating structures are added to isolate modules and prevent cross-talk, then noise immunity improves, but device complexity increases
Solution Approach 1:
The patent introduces insulating structures (such as insulating layers or trenches filled with insulating material) as intermediary elements between adjacent potential wells. These insulating structures effectively isolate the digital, analog, and power circuits from each other, preventing cross-talk and substrate potential fluctuations, while being integrated into the standard CMOS fabrication process to avoid excessive complexity.
3Reliability
If a non-monocrystalline semiconductor layer is used to absorb pulses, then reliability against ESD improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the material parameter of the semiconductor layer from monocrystalline to non-monocrystalline (such as polycrystalline or amorphous silicon) in specific regions. This parameter change enables the layer to absorb ESD pulses and energetic electric pulses more effectively, protecting the sensitive circuits. The non-monocrystalline layer can be deposited using standard semiconductor fabrication techniques like CVD or sputtering, which are well-established and controllable processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces cross-talk between modules, enhances reliability by isolating noise sources, and maintains heat dissipation, thereby improving the robustness of semiconductor devices against ESD and energetic electric pulses.
Implementation Method 1
An insulating region insulates the first well and the silicon layer from one another and insulates the first and second wells from one another
Data Source
AI summary
An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.