Semiconductor Interconnection Insulating Pattern for Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices become more integrated, the increasing distances between patterns and contact plugs lead to increased parasitic capacitance, which deteriorates performance and operation speed due to the small size and multifunctional nature of these devices.
Innovation Solution
A semiconductor device design that includes a substrate with a cell region and a peripheral region, featuring a gate stack, interlayer insulating layers, peripheral circuit interconnection lines, and an interconnection insulating pattern with vertical and connecting portions, which are strategically positioned to reduce parasitic capacitance by maintaining uniform thickness and overlapping with device isolation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the integration density of semiconductor devices increases, then the size of devices decreases and functionality increases, but the distance between patterns and contact plugs decreases leading to increased parasitic capacitance
Solution Approach 1:
An interconnection insulating pattern is introduced as an intermediary element between peripheral circuit interconnection lines. This insulating pattern includes vertical portions positioned adjacent to the interconnection lines, creating an insulating barrier that reduces parasitic capacitance between the lines and underlying structures, thereby resolving the capacitance issue while maintaining high integration density
Solution Approach 2:
The solution transitions from two-dimensional planar insulation to three-dimensional vertical insulation structures. The interconnection insulating pattern extends vertically with specific thickness dimensions, creating insulation in the vertical dimension rather than relying solely on horizontal spacing, thus reducing parasitic capacitance without increasing device footprint
2Area of stationary object
If peripheral circuit interconnection lines are placed closer together to increase integration, then device size decreases, but parasitic capacitance between lines increases
Solution Approach 1:
The interconnection insulating pattern serves as a mediator between adjacent peripheral circuit interconnection lines. By positioning vertical portions of the insulating pattern adjacent to the interconnection lines, it creates an insulating barrier that reduces electrostatic coupling and parasitic capacitance between closely spaced lines
Solution Approach 2:
The interconnection insulating pattern is formed using a composite structure including a lower interconnection insulating pattern and an upper interconnection insulating pattern at different vertical levels. This multi-layer composite approach provides comprehensive insulation coverage, effectively reducing parasitic capacitance while maintaining compact device geometry
Data Source
AI summary
A semiconductor device may include a substrate including a cell region and a peripheral region, a gate stack on the peripheral region, an interlayer insulating layer on the gate stack, peripheral circuit interconnection lines on the interlayer insulating layer, and an interconnection insulating pattern between the peripheral circuit interconnection lines. The interconnection insulating pattern may include a pair of vertical portions spaced apart from each other in a first direction parallel to a top surface of the substrate and a connecting portion connecting the vertical portions to each other. Each of the vertical portions of the interconnection insulating pattern may have a first thickness at a same level as top surfaces of the peripheral circuit interconnection lines and a second thickness at a same level as bottom surfaces of the peripheral circuit interconnection lines. The first thickness may be substantially equal to the second thickness.