Semiconductor Structure With Insulating Via For SSRW
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Solution Overview
Problem
Short-channel effects in semiconductor devices, such as MOSFETs, lead to deteriorated electrical properties, increased power consumption, and reduced Signal-to-Noise Ratio, which are challenging to address with traditional manufacturing processes, especially in three-dimensional device structures like FinFETs, where maintaining thin silicon layers and controlling doping profiles is difficult.
Innovation Solution
A semiconductor structure and manufacturing method that involves forming a void in the semiconductor base and embedding an insulating via to create a Super-Steep Retrograde Well (SSRW) with a heavily doped epitaxial layer, along with adjusting stress through the insulating via to improve carrier mobility, while simplifying the process by reducing the number of mask plates and enhancing gate placement to increase effective channel areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is used to form heavily doped regions, then doping profile can be created, but it is difficult to control doping profile and grow epitaxial layer at heavily doped region
Solution Approach 1:
The patent forms a sacrificial layer before epitaxial growth, which is subsequently removed to create voids. This preliminary action prepares the structure for selective epitaxial growth in the voids, avoiding the difficulty of growing epitaxial layers directly on heavily doped regions while achieving precise doping profile control through the sacrificial layer pattern
2Reliability
If silicon layer thickness is reduced to manufacture FD devices, then depletion regions can fill channel completely, but it is hard to manufacture desired structure and costs considerably high
Solution Approach 1:
The patent transitions from planar FD device structure to three-dimensional FinFET structure with vertical channels. This dimensional change allows the channel to be fully depleted while maintaining manufacturability through self-aligned processes and standard thickness silicon layers, avoiding the high cost and difficulty of manufacturing ultra-thin planar FD devices
3Speed
If gate oxide thickness is thinned to keep pace with gate width reduction, then device speed improves, but gate dielectric leakage increases
Solution Approach 1:
The patent employs a composite gate dielectric structure consisting of multiple layers with different materials and functions. This composite structure provides both the thinness required for high-speed operation and the leakage control through material selection and layer configuration, resolving the contradiction between speed and leakage
4Ease of manufacture
If traditional planar device structure is used, then manufacturing is simpler, but depletion regions cannot fill channel completely and short-channel effects persist
Solution Approach 1:
The patent adopts a three-dimensional FinFET structure where the gate wraps around the channel in multiple dimensions. This dimensional change enables complete channel depletion while maintaining manufacturing simplicity through self-aligned processes, overcoming the limitations of traditional planar devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses short-channel effects, improves carrier mobility, reduces resistance, and lowers manufacturing costs by forming a super-steep retrograde doping profile and adjusting stress in channel regions, thereby enhancing device performance.
Implementation Method 1
forming an epitaxial layer within the void through selective epitaxial method
Implementation Method 2
adjusting stress through the insulating via to improve carrier mobility
Data Source
AI summary
The present invention provides a semiconductor structure comprising: a semiconductor base located on an insulating layer, wherein the insulating layer is located on a semiconductor substrate; source/drain regions, which are in contact with first sidewalls of the semiconductor base opposite to each other; gates located on second sidewalls of the semiconductor base opposite to each other; an insulating via located on the insulating layer and embedded into the semiconductor base; and an epitaxial layer sandwiched between the insulating via and the semiconductor base. The present invention further provides a method for manufacturing a semiconductor structure comprising: forming an insulating layer on a semiconductor substrate; forming a semiconductor base on the insulating layer; forming a void within the semiconductor base, wherein the void exposes the semiconductor substrate; forming an epitaxial layer in the void through selective epitaxy; and forming an insulating via within the void. Short-channel effects are significantly suppressed through forming super-steep retrograde well (SSRW).