Semiconductor Insulation Structures for Etch-Resistant FinFET Isolation
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in maintaining the integrity of insulation features during fabrication, particularly in forming insulation structures like Continuous Poly On Diffusion Edge (CPODE) and Continuous Metal On Diffusion Edge (CMODE), which require precise etching to avoid degradation and ensure compatibility with adjacent layers.
Innovation Solution
The method involves controlled etching processes to remove upper portions of sidewall spacers and adjacent ILD structures, forming insulation features with minimized liner thickness and materials that do not degrade during subsequent etching, ensuring compatibility with dielectric structures and preventing etching into insulation features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but the integrity of insulation features deteriorates due to difficulties in maintaining precision during fabrication
Solution Approach 1:
The patent applies preliminary action by forming the insulation feature before subsequent etching processes. The method involves depositing insulation material conformally over the substrate and then performing selective etching to define the insulation feature geometry. This preliminary formation ensures the insulation feature is in place before any potentially degrading etching operations occur on adjacent structures.
Solution Approach 2:
The patent uses an intermediary approach by introducing a controlled etching process that selectively removes material only where needed while protecting the insulation feature. The etching process acts as an intermediary step that shapes the surrounding structures without compromising the insulation feature's integrity, using appropriate etching conditions and selectivity to prevent degradation.
2Manufacturing precision
If controlled etching processes are used to remove upper portions of sidewall spacers and adjacent ILD structures, then insulation features can be formed with minimized liner thickness, but the risk of etching degradation increases
Solution Approach 1:
The patent applies parameter changes by carefully controlling etching parameters such as etchant composition, temperature, pressure, and exposure time to achieve selective removal of sidewall spacer and ILD material while preserving the insulation feature. The method optimizes these parameters to minimize liner thickness while preventing etching degradation through precise parameter selection and process sequencing.
3Manufacturing precision
If insulation features are formed with minimized liner thickness, then manufacturing precision is improved, but the features become more susceptible to etching attacks from subsequent processes
Solution Approach 1:
The patent applies preliminary anti-action by designing the insulation feature formation process to preemptively protect against subsequent etching attacks. The method involves forming the insulation feature with optimized geometry and material properties before any harmful etching processes occur, and sequencing operations to ensure that etching processes used for other structures do not adversely affect the insulation feature.
Data Source
AI summary
Semiconductor devices with insulation structures and methods of fabrication are provided. A method includes forming fins over a substrate; forming a gate over the fins, wherein a sidewall spacer is laterally adjacent to the gate; removing an upper portion of the sidewall spacer; forming a cavity by removing a selected segment of the gate and removing a selected fin located under the selected segment; and forming an insulation feature in the cavity.