Semiconductor Integrated Circuit Parasitic Capacitance Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The charge transfer efficiency in semiconductor integrated circuits, such as NAND-type flash memory, is reduced due to parasitic capacitances generated by the layout of upper layer wirings, which decreases the performance of boosting circuits used in peripheral circuits.
Innovation Solution
The arrangement of transfer transistors and capacitors is optimized by using a specific configuration of metal wirings and clock pulse supply lines, which includes a planar lower layer wiring and an upper layer wiring that functions as both a clock pulse supplier and a shield, reducing parasitic capacitances and enhancing charge transfer efficiency without increasing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If upper layer wirings are laid out in conventional manner, then chip size is reduced, but parasitic capacitances increase and charge transfer efficiency decreases
Solution Approach 1:
The patent converts the harmful parasitic capacitances generated by upper layer wirings into beneficial effects. Specifically, the clock signal line in the upper layer is intentionally positioned to overlap with the gate electrode, transforming the parasitic capacitance between the clock signal line and gate electrode into a useful capacitance that assists in driving the transfer transistor. This converts a harmful factor (parasitic capacitance) into a beneficial element that improves charge transfer efficiency.
Solution Approach 2:
The upper layer wiring serving as the clock signal line performs multiple functions: it supplies the clock signal to the capacitor and simultaneously generates beneficial parasitic capacitance with the gate electrode due to intentional overlapping. This multi-functional design allows the same wiring structure to serve both signal distribution and capacitance generation purposes, improving efficiency without additional components.
2Productivity
If capacitor capacity is increased to improve boosting performance, then charge transfer efficiency improves, but chip area increases
Solution Approach 1:
The patent generates beneficial parasitic capacitance by intentional overlapping of the clock signal line with the gate electrode, converting what would normally be a harmful parasitic effect into a useful capacitance source. This additional capacitance contributes to the total capacitance available for charge transfer, improving efficiency without requiring larger dedicated capacitor structures.
Solution Approach 2:
The patent merges the function of the clock signal line with the function of capacitance generation. The upper layer clock signal line not only supplies timing signals but also serves as a capacitance source through its overlapping configuration with the gate electrode. This consolidation eliminates the need for separate capacitance structures, reducing overall chip area while maintaining or improving charge transfer efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the total capacity between transfer nodes and input nodes, leading to improved charge transfer efficiency and reduced gate voltage rise, while maintaining a compact design without increasing chip size, thus enhancing the performance of semiconductor integrated circuits.
Implementation Method 1
parasitic capacitances generated by the layout of upper layer wirings
Data Source
AI summary
A semiconductor integrated circuit according to an embodiment includes a transfer transistor including a first gate electrode, the first gate electrode and a diffusion layer being diode-connected with a first wiring, and a clock signal line to which a clock signal is supplied, at least a portion of a first partial clock signal line, which is a portion of the clock signal line, being formed above the first gate electrode.