Semiconductor Integrated Circuit Design Harmonizing Vertical and Lateral Elements
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Solution Overview
Problem
Existing semiconductor integrated circuits fail to efficiently harmonize the characteristics of vertical output stage elements and lateral circuit elements on the same chip, leading to suboptimal performance and increased manufacturing costs.
Innovation Solution
A semiconductor integrated circuit design that includes a support layer, well regions, buried layers, and terminal regions with specific conductivity types and impurity concentrations, along with a control electrode structure, to effectively control the output stage element, and a method of manufacturing that forms these regions to optimize both vertical and lateral element characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a power IC integrates vertical MOSFET and lateral MOSFET on the same chip, then miniaturization and cost reduction are achieved, but efficient harmonization of characteristics between output stage element and circuit element is not considered
Solution Approach 1:
The patent applies local quality by providing different impurity concentration configurations in different regions: the circuit element has a well region with impurity concentration of 1×10^16 to 1×10^18 atoms/cm³, while the output stage element has a body region with impurity concentration of 1×10^14 to 1×10^16 atoms/cm³. This localized differentiation allows each element to operate at its optimal characteristics while being integrated on the same chip, resolving the contradiction between miniaturization and characteristic harmonization.
2Ease of manufacture
If vertical MOSFET and lateral MOSFET are monolithically integrated, then manufacturing cost is reduced, but manufacturing complexity increases due to multiple diffusion processes
Solution Approach 1:
The patent merges the formation of well region and body region into a single ion implantation step, where both regions are formed simultaneously with different impurity concentrations. The circuit side buried layer and output side buried layer are also formed in the same process step. This consolidation of multiple diffusion processes into one step reduces manufacturing complexity while maintaining the ability to produce both element types on the same chip, thereby reducing overall manufacturing cost.
3Reliability
If well region and body region have different impurity concentrations, then characteristics of circuit element and output stage element are optimized, but device structure complexity increases
Solution Approach 1:
The patent utilizes parameter changes by precisely controlling impurity concentrations in different regions: the well region is doped at 1×10^16 to 1×10^18 atoms/cm³ while the body region is doped at 1×10^14 to 1×10^16 atoms/cm³. The circuit side buried layer and output side buried layer also have specifically controlled impurity concentrations. These parameter variations enable optimal characteristics for both circuit and output stage elements. The complexity is managed by implementing these parameter changes in a single ion implantation process rather than multiple separate steps.
Data Source
AI summary
A method of manufacturing a semiconductor integrated circuit includes forming a body region having a second conductivity type in an upper portion of a support layer having a first conductivity type and forming a well region having a second conductivity type in an upper portion of the support layer. An output side buried layer is formed inside the body region and a circuit side buried layer is formed inside the well region. A trench is dug to penetrate through the body region and a control electrode structure is buried in the gate trench. First and second terminal regions are formed on the well region and an output terminal region is formed on the body region. An output stage element having the output terminal region is controlled by a circuit element including the first and second terminal regions.