Semiconductor Integrated Circuit Power-On Precharge
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Solution Overview
Problem
Conventional EEPROM modules have a long chip reset period and increased module size due to the need for internal oscillators and complex control circuits for reading trimming information, making them unsuitable for applications requiring immediate power-on validation and compact designs.
Innovation Solution
A semiconductor integrated circuit device with a power-on precharge circuit that precharges the data line before releasing the power-on reset, allowing for immediate reading of trimming information and reducing module size by eliminating unnecessary components like internal oscillators and control circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional EEPROM modules use internal oscillators and complex control circuits for reading trimming information, then the reading operation can be performed, but the chip reset period becomes long and module size increases
Solution Approach 1:
The patent applies preliminary action by precharging the data line before the power-on reset is released. The data line precharge circuit activates first to prepare the data line, and only after this precharge is complete does the power-on reset release to enable trimming information reading. This sequencing eliminates the need for complex control circuits and internal oscillators, directly reducing both the chip reset period and module size.
2Reliability
If conventional EEPROM modules use internal oscillators and control circuits for reading trimming information, then the reading operation can be performed, but the module size increases
Solution Approach 1:
The patent extracts and removes unnecessary components (internal oscillators and complex control circuits) from the module. By using a simplified data line precharge circuit that activates automatically on power-on, the design eliminates components that do not contribute to the essential function of reading trimming information, thereby reducing module size while maintaining power-on validation reliability.
3Device complexity
If the data line is not precharged before power-on reset release, then the circuit can be simplified, but the reading operation of trimming information cannot be completed properly
Solution Approach 1:
The patent ensures proper reading operation by implementing preliminary precharge action on the data line. The data line precharge circuit activates automatically when power is applied, preparing the data line before the power-on reset releases. This simple yet effective preliminary action maintains reading reliability without requiring complex control circuits.
Data Source
AI summary
A semiconductor integrated circuit device capable of shortening a chip reset period (time) is provided. The semiconductor integrated circuit device has a nonvolatile memory which performs a reading operation of trimming information after completion of precharge of a data line, and a power-on reset circuit (64) which starts an operation in response to power-on to reset a control circuit of the nonvolatile memory. The device further has a power-on precharge circuit (66) which starts an operation in response to the power-on to perform the precharge operation of the data line. The power-on reset circuit (64) includes a first CR operation circuit (642) which produces a reset release signal indicative of change of a voltage level at a time point when a first predetermined time period (T1) elapses from the power-on. The power-on precharge circuit (66) includes a second CR operation circuit (662) which produces a precharge completion signal indicative of change of a voltage level at a time point when a second predetermined time period (T2) elapses from the power-on. The first predetermined time period (T1) is longer than the second predetermined time period (T2).