Semiconductor Integrated Circuit Parasitic Thyristor Suppression
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in suppressing parasitic thyristor operation while maintaining a small chip area and controlling process costs, as previous methods either increase chip area or are ineffective against instantaneous potential swings during noise applications.
Innovation Solution
The semiconductor integrated circuit design includes a semiconductor substrate with high and low-potential side circuit areas, where the low-potential side circuit area has a higher impurity concentration than the high-potential side well region, and a third well region with an impurity concentration equal to or lower than the first well region, allowing for effective separation and reduced parasitic thyristor operation without increasing chip area or process costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the low-side n well and high-side p well are arranged so as to be separated from each other to suppress parasitic thyristor operation, then the parasitic thyristor operation is suppressed, but the chip area is increased
Solution Approach 1:
The patent changes the impurity concentration parameter of the low-side n well, setting it to be equal to or higher than the high-side n well. This parameter change modifies the electrical characteristics of the parasitic thyristor structure, suppressing latch-up operation without requiring increased spatial separation between wells, thereby maintaining small chip area while improving reliability
2Reliability
If conventional methods are used to suppress parasitic thyristor operation, then some level of suppression is achieved, but the methods are ineffective against instantaneous potential swings during noise applications
Solution Approach 1:
The patent modifies the impurity concentration parameter of the low-side n well to be equal to or higher than the high-side n well. This parameter change raises the potential barrier for parasitic thyristor activation, making the structure effective against instantaneous potential swings caused by noise. The solution maintains simplicity by using a single parameter change rather than adding complex isolation structures
Solution Approach 2:
The patent establishes the low-side n well impurity concentration to be equal to or higher than the high-side n well before noise interference occurs. This preliminary configuration of impurity concentration creates a potential barrier that proactively prevents parasitic thyristor activation during noise events, rather than attempting to suppress latch-up after it begins
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses parasitic thyristor operation with a smaller chip area and reduced process costs, maintaining stability even during instantaneous potential swings, thereby enhancing the reliability and efficiency of the semiconductor integrated circuit.
Implementation Method 1
a first well region having a second conductivity type, which is provided in an upper part of the semiconductor substrate in a high-potential side circuit area defined in the semiconductor substrate; a second well region having the first conductivity type, which is provided in an upper part of the first well region and has an impurity concentration higher than an impurity concentration of the semiconductor substrate
Data Source
AI summary
A semiconductor integrated circuit includes: a p−-type semiconductor substrate defining a high-potential side circuit area and a low-potential side circuit area separated from each other; a high-side n well provided in an upper part of the semiconductor substrate in the high-potential side circuit area; a high-side p well provided in the high-side n well; and a p-type semiconductor region provided in an upper part of the semiconductor substrate in the low-potential side circuit area; and n+-type semiconductor region provided to be brought contact with the p-type semiconductor region, wherein a whole n-type semiconductor region including the n+-type semiconductor region, has an impurity concentration higher than an impurity concentration of the high-side n well.