Semiconductor Integrated Circuit Timing Control
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Solution Overview
Problem
In semiconductor integrated circuits, successive read commands to one memory bank can cause a drop in power supply voltage, leading to timing errors in input control signals, which results in overlapping timing signals for accessing different memory banks, causing read operation errors.
Innovation Solution
A semiconductor integrated circuit with a latch unit and latch control unit that adjusts the timing of input control signals based on the number of successive accesses to memory banks, using a delay control signal generation unit and source signal generation unit to generate delay control signals and adjust the timing of source signals, preventing overlap and ensuring stable data latch operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If successive read commands are applied to one memory bank, then data output speed is improved, but power supply voltage drops causing timing signal overlap and read operation errors
Solution Approach 1:
The patent applies dynamics by making the delay time of the input control signal adjustable rather than fixed. The delay control unit dynamically changes the delay time based on the access pattern detection result, increasing delay when successive reads to one bank are followed by a read to the other bank, and reducing delay during normal successive reads. This dynamic adjustment resolves the contradiction by maintaining timing accuracy under varying operational conditions while preserving high-speed data output.
Solution Approach 2:
The patent implements feedback through the access pattern detection unit that continuously monitors read command patterns and provides feedback to the delay control unit. When the detection unit identifies a specific pattern (successive reads to one bank followed by a read to the other), it triggers the delay control unit to adjust the timing. This feedback mechanism resolves the contradiction by automatically adapting the timing strategy based on actual operational patterns, preventing timing overlap while maintaining high productivity during normal operation.
2Reliability
If delay time of input control signal is increased to prevent timing overlap, then read operation accuracy is improved, but data output speed decreases
Solution Approach 1:
The patent applies dynamics by making the delay time of the input control signal adjustable rather than fixed. The delay control unit dynamically changes the delay time based on the access pattern detection result, increasing delay when successive reads to one bank are followed by a read to the other bank, and reducing delay during normal successive reads. This dynamic adjustment resolves the contradiction by maintaining timing accuracy under varying operational conditions while preserving high-speed data output.
Solution Approach 2:
The patent applies local quality by applying delay adjustment only to specific control signals under specific conditions rather than uniformly to all signals. The delay control unit selectively increases delay time only for the input control signal when the access pattern detection unit identifies the problematic pattern (successive reads to one bank followed by a read to the other). This localized approach resolves the contradiction by correcting timing issues only where necessary, maintaining high productivity during normal operations.
3Reliability
If timing of input control signal is adjusted dynamically, then timing signal overlap is prevented, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the latch control functionality into separate modular units: an access pattern detection unit that monitors read commands, and a delay control unit that adjusts timing based on detection results. This segmentation resolves the contradiction by distributing the complexity across specialized modules rather than concentrating it in a single complex control unit, making the system more manageable and maintainable while achieving reliable timing separation.
Data Source
AI summary
A semiconductor integrated circuit includes: a latch unit configured to latch data in response to an input control signal; and a latch control unit configured to determine whether or not any one of first and second memory areas is successively accessed, and adjust timing of the input control signal.