Semiconductor Package with Integrated Electrode Terminals
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving a low-cost, downsized package with extended life, particularly in large-capacity modules, due to stress issues from current imbalances and thermal expansion differences in power device chips.
Innovation Solution
A semiconductor device design featuring a substrate with metallic patterns, semiconductor chips mounted on these patterns, back and front surface electrode terminals connected via wires and solder, and a sealing case with a resilient seal material to manage thermal stress and reduce package size and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect electrode parts with wires, then electrical connectivity is achieved, but the package size increases and life decreases due to stress from cold heat cycles
Solution Approach 1:
The patent combines the back surface electrode terminal and front surface electrode terminal into a single integrated terminal structure that extends from the back surface through the case to the front surface. This merging eliminates the need for separate wire connections and reduces the number of stress-prone junctions, thereby improving reliability while minimizing package size.
Solution Approach 2:
The patent introduces a case with a resilient seal material as an intermediary between the electrode terminals and the external environment. This intermediary structure absorbs thermal expansion differences and stress from cold heat cycles, protecting the wire bonding junctions and extending their life without increasing package size.
2Reliability
If wire bonding is used for connecting electrodes, then electrical connectivity is achieved, but manufacturing cost increases
Solution Approach 1:
The integrated terminal structure reduces the number of separate components and assembly steps required. By combining the back surface and front surface electrode terminals into one piece, the patent simplifies manufacturing and reduces costs while maintaining the reliability benefits of reduced thermal stress on junctions.
3Volume of stationary object
If package size is reduced for downsizing, then cost is reduced, but stress from thermal expansion differences increases
Solution Approach 1:
The patent employs a case with a resilient seal material that acts as a flexible element capable of accommodating thermal expansion differences between components. This flexible structure absorbs stress during thermal cycling, allowing for package downsizing without compromising reliability.
Solution Approach 2:
The resilient seal material changes its physical parameters (such as elasticity and damping properties) in response to thermal stress, allowing it to absorb and dissipate energy from thermal expansion differences. This parameter change enables the package to maintain small size while resisting thermal stress.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the life and reliability of semiconductor devices by reducing thermal stress, minimizing package size, and lowering manufacturing costs while ensuring effective sealing and electrical connectivity.
Implementation Method 1
a back surface electrode terminal in flat plate form connected to the metallic pattern with a wire
Implementation Method 2
a seal material for sealing an inside of the case
Data Source
AI summary
According to the present invention, a semiconductor device includes a substrate having a metallic pattern formed on a top surface of the substrate, a semiconductor chip provided on the metallic pattern, a back surface electrode terminal in flat plate form connected to the metallic pattern with a wire, a front surface electrode terminal in flat plate form, the front surface electrode terminal being in parallel to the back surface electrode terminal above the back surface electrode terminal, extending immediately above the semiconductor chip, and being directly joined to a top surface of the semiconductor chip, a case surrounding the substrate and a seal material for sealing an inside of the case.