Semiconductor Device Integrating Multiple Circuit Elements

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Solution Overview

Problem

The challenge lies in manufacturing semiconductor devices that can integrate multiple types of circuit elements, such as lateral bipolar transistors, zener diodes, and LDMOS field effect transistors, without significantly increasing the manufacturing processes or costs, as existing methods require multiple masks and processes for each type of circuit element.

Innovation Solution

A semiconductor device and manufacturing method that utilize a common basic structure of buried diffusion layers and impurity diffusion regions in the semiconductor substrate, allowing for the simultaneous formation of various circuit elements like lateral and vertical bipolar transistors, zener diodes, and LDMOS field effect transistors, by forming multiple impurity diffusion regions and wells in a single process step.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple dedicated impurity diffusion regions are formed for different circuit elements, then the functionality and versatility of the semiconductor device is improved, but the manufacturing complexity and cost increase due to increased number of masks and processes

Engineering Contradiction:
ImprovefunctionalityVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing a common basic structure consisting of buried diffusion layers and impurity diffusion regions that can serve multiple circuit element types. The same structural components are used to form lateral bipolar transistors, zener diodes, and LDMOS field effect transistors, allowing one structure to perform multiple functions and reducing the need for dedicated structures for each element type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the formation of multiple impurity diffusion regions and wells into a single process step. By combining the creation of various doped regions that will later serve different circuit elements into one simultaneous implantation process, the manufacturing complexity is reduced while still achieving the desired functionality of multiple element types.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If multiple dedicated impurity diffusion regions are formed for different circuit elements, then the functionality and versatility of the semiconductor device is improved, but the manufacturing cost increases due to increased number of masks and processes

Engineering Contradiction:
ImprovefunctionalityVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent applies universality by designing a common basic structure consisting of buried diffusion layers and impurity diffusion regions that can serve multiple circuit element types. The same structural components are used to form lateral bipolar transistors, zener diodes, and LDMOS field effect transistors, allowing one structure to perform multiple functions and reducing the need for dedicated structures for each element type.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the formation of multiple impurity diffusion regions and wells into a single process step. By combining the creation of various doped regions that will later serve different circuit elements into one simultaneous implantation process, the manufacturing complexity is reduced while still achieving the desired functionality of multiple element types.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If multiple dedicated impurity diffusion regions are formed for different circuit elements, then the functionality and versatility of the semiconductor device is improved, but the number of manufacturing processes increases

Engineering Contradiction:
ImprovefunctionalityVSAvoidmanufacturing efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent merges the formation of multiple impurity diffusion regions and wells into a single process step. By combining the creation of various doped regions that will later serve different circuit elements into one simultaneous implantation process, the manufacturing complexity is reduced while still achieving the desired functionality of multiple element types.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the integration of multiple circuit elements on a single semiconductor device using a common structure, reducing the complexity and cost of manufacturing by minimizing the number of required processes, while maintaining the desired electrical characteristics of each circuit element.

Implementation Method 1

forming a second conductivity type first impurity diffusion region that is arranged in the semiconductor layer and surrounds a first region of the semiconductor layer on the first buried diffusion layer in plan view; forming a second conductivity type second impurity diffusion region that is arranged, in the semiconductor layer, on the second buried diffusion layer

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS10541299B2Semiconductor device and manufacturing method thereof
Publication Date: 2020.01.21 SEIKO EPSON CORP
  • US10541299B2 patent drawing
  • US10541299B2 patent drawing
  • US10541299B2 patent drawing

AI summary

A semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first and second buried diffusion layers that are arranged in the semiconductor substrate, a semiconductor layer arranged on the semiconductor substrate, a second conductivity type first impurity diffusion region that is arranged in the semiconductor layer, a second conductivity type second impurity diffusion region that is arranged, in the semiconductor layer, on the second buried diffusion layer, a second conductivity type first well that is arranged in a first region of the semiconductor layer, a first conductivity type second well that is arranged, in the semiconductor layer, in a second region, a first conductivity type third and fourth impurity diffusion regions that are arranged in the first well, and a first conductivity type fifth impurity diffusion region that is arranged in the second well.