Semiconductor Interconnect Layout for Lower Contact Resistance
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Solution Overview
Problem
The challenge of reducing contact resistances in interconnect structures of semiconductor devices, particularly in logic areas like SRAM, becomes increasingly difficult as critical dimensions of dielectric spacing are shrunk, complicating IC processing and increasing fabrication costs.
Innovation Solution
The method involves forming a patterned structure with a narrower width to enlarge the critical dimension of interconnect structures, reducing contact resistances by trimming the dielectric spacing between adjacent interconnect structures in FinFET devices, which includes forming fins, isolation regions, and gate structures, and using sacrificial helmet structures to protect the active gate while creating contact holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the critical dimensions of dielectric spacing are shrunk to increase functional density, then the number of interconnected devices per chip area increases, but the contact resistances of interconnect structures increase and device performance deteriorates
Solution Approach 1:
The patent applies local quality by creating a tapered profile in the interconnect structure where the width varies along the depth. The interconnect is wider at the top surface and narrower at the bottom, allowing the contact opening to be enlarged at the top region where it interfaces with the pad, thereby reducing contact resistance locally without increasing the overall critical dimension of the dielectric spacing.
Solution Approach 2:
The patent resolves the contradiction by transitioning from a two-dimensional planar constraint to a three-dimensional tapered structure. Instead of simply enlarging the contact opening in the planar view (which would increase dielectric spacing), the solution creates a vertical dimension variation with a tapered profile, allowing the contact opening to be larger at the top while maintaining tight spacing at the bottom.
2Productivity
If the critical dimensions of dielectric spacing are shrunk to increase functional density, then the number of interconnected devices per chip area increases, but the IC processing complexity increases and fabrication costs rise
Solution Approach 1:
The patent applies preliminary action by forming the tapered profile of the interconnect structure before creating the contact opening. The tapered profile is established in the interlayer dielectric and conductive material layers during earlier processing steps, which then guides the subsequent contact hole formation process and simplifies the overall fabrication sequence.
Data Source
AI summary
A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.