Semiconductor Interconnect Vertical Structure for Current Crowding Relief
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Solution Overview
Problem
Current semiconductor devices face challenges in maintaining high electrical and reliability characteristics due to excessive current crowding and high resistance in interconnection lines, particularly in structures with merged current paths, leading to instability and performance deterioration.
Innovation Solution
The semiconductor device incorporates a vertical structure with multiple unit structures that provide separate current paths, including interconnection lines in both the n-th and (n−2)-th metal layers, allowing for efficient current distribution and reducing current crowding by merging currents at specific points, thereby improving stability and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current paths are merged in conventional interconnection structures, then device integration is achieved, but current crowding and high resistance occur leading to electrical characteristic deterioration
Solution Approach 1:
The interconnection layer is divided into multiple metal layers (first through fourth metal layers) with distinct functions. The first metal layer handles vertical interconnection via vias, the second metal layer provides horizontal interconnection, and the third/fourth metal layers provide alternative current paths. This segmentation distributes current flow across multiple layers, preventing current crowding and reducing resistance in any single path.
Solution Approach 2:
The patent transitions from planar (2D) interconnection to three-dimensional (3D) stacked metal layers. By adding the vertical dimension with multiple stacked metal layers, the patent creates additional current paths that do not interfere with each other, effectively reducing current crowding and resistance while maintaining compact device footprint.
2Power
If interconnection lines are designed to carry high current, then driver cell performance improves, but resistance and instability increase
Solution Approach 1:
Multiple interconnection lines from different metal layers are merged at via structures to combine current paths. The first interconnection line from the second metal layer and the second interconnection line from the third metal layer are merged through vias to reach the fourth metal layer, creating parallel current paths that share the current load, thereby reducing resistance and improving stability.
Solution Approach 2:
The via structures serve multiple functions: they act as vertical interconnection elements, current merging points, and current distribution nodes. Each via both connects different metal layers and serves as a junction where current paths converge and diverge, enabling flexible current management across the interconnection network.
3Reliability
If multiple current paths are provided through separate vertical structures, then current crowding is reduced, but device area increases
Solution Approach 1:
Multiple interconnection lines are nested vertically across stacked metal layers rather than being placed side-by-side in the planar direction. The first, second, third, and fourth metal layers are stacked one above another, with interconnection lines at different heights, effectively nesting multiple current paths within a compact vertical space, thereby reducing the device area footprint.
Data Source
AI summary
A semiconductor device includes a logic cell region on a substrate, an interconnection layer on the logic cell region, the interconnection layer including a plurality of metal layers on the logic cell region, and a first vertical structure in the interconnection layer, where the first vertical structure vertically connects the logic cell region to an uppermost metal layer of the plurality of metal layers, each of the plurality of unit structures includes a lower via, a lower interconnection line, an upper via, and an upper interconnection line, the lower interconnection line and the upper interconnection line of each respective unit structure of the plurality of unit structures cross each other, and the upper interconnection line of each of the plurality of unit structures includes a first upper interconnection line.