Semiconductor Interconnect Layout for Uniform Transistor Current Density
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Solution Overview
Problem
Existing semiconductor devices with two-dimensional transistor arrangements face challenges in achieving uniform current densities due to high current densities at the boundaries of conductive layers, leading to potential degradation from electromigration.
Innovation Solution
A semiconductor device configuration with a transistor layer having interconnection layers and interlayer connection conductors, where the resistance values of the interlayer connection conductors differ based on their position, ensuring uniform current distribution across the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the size of transistors is reduced to lower device cost, then manufacturing cost is reduced, but current density in metal interconnection layers increases causing electromigration degradation
Solution Approach 1:
The patent applies local quality by varying the resistance values of interlayer connection conductors based on their spatial position within the transistor array. Conductors closer to boundary regions have different resistance characteristics than those in central regions, creating localized property variations that compensate for non-uniform current distribution patterns and prevent electromigration in high-stress areas
2Productivity
If transistors are arranged in a two-dimensional distributed manner to increase integration density, then device functionality is improved, but current density uniformity deteriorates due to boundary effects in conductive layers
Solution Approach 1:
The patent implements local quality by assigning different resistance values to interlayer connection conductors based on their positions within the two-dimensional transistor array. This creates localized electrical characteristics that compensate for boundary effects, ensuring uniform current density distribution across the entire transistor array while maintaining high integration density
Solution Approach 2:
The patent applies parameter changes by systematically varying the resistance values of interlayer connection conductors as a function of their spatial position. This parameter variation compensates for the non-uniform current distribution that arises from boundary effects in two-dimensional transistor arrangements, achieving uniform current density across all transistors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively achieves uniform current densities across transistors, reducing the risk of electromigration-induced degradation and allowing for a more reliable and cost-effective semiconductor device.
Implementation Method 1
resistance values of the plurality of interlayer connection conductors differ from each other depending on a position in the arranging direction
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
There is a disadvantage in which current densities cannot be uniform in the entire region of transistors arranged to be distributed in a two-dimensional manner. On a transistor layer having arranged thereon multiple transistors 1 each including a drain, a source, and a gate, metal interconnection layers 10 serving as input side interconnection layers connected to the drains of the respective transistors 1 and metal interconnection layers 11 serving as output side interconnection layers connected to the sources of the respective transistors are arranged in parallel. Also provided are a plurality of through holes 2 and 3 connecting the metal interconnection layers 10 serving as input side interconnection layers to the drains of the respective transistors and connecting the metal interconnection layers 11 serving as output side interconnection layers to the sources of the respective transistors. Resistance values of the plurality of through holes 2 and 3 are changed along an arranging direction of the input side interconnection layers and the output side interconnection layers. Accordingly, current densities of the transistors arranged to be distributed in a two-dimensional manner can be uniform.