Semiconductor Interconnect Layout for Dense Low-Resistance Routing
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Solution Overview
Problem
The challenge in integrated circuit design is the lack of routing resources, particularly for achieving smaller chip area and better performance, due to complex process rules.
Innovation Solution
An optimized layout and metal structure are introduced, incorporating Fin Field-Effect Transistors (FinFETs) and Gate All Around (GAA) transistors, with a multilayer interconnection structure that includes metal layers with varying thickness and pitch to enhance routing efficiency and reduce intra-cell coupling capacitance and power line resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional routing structures are used, then routing resources are sufficient for basic connections, but routing efficiency is low and chip area increases
Solution Approach 1:
The patent transitions from planar 2D routing to 3D vertical routing by stacking multiple metal layers with different thicknesses. The interconnection structure utilizes vertical vias to connect horizontal metal traces across multiple layers, enabling signals to route in the vertical dimension rather than being constrained to single-layer horizontal paths. This dimensional expansion dramatically increases routing capacity without proportionally increasing chip footprint.
Solution Approach 2:
The routing structure is divided into multiple segmented metal layers (first metal layer, second metal layer, third metal layer) with varying thicknesses and pitches. Each layer is optimized for specific routing functions, with thinner layers for dense local connections and thicker layers for power delivery and long-distance signals. This segmentation allows independent optimization of each layer's routing resources.
2Reliability
If metal layer thickness is increased to reduce resistance, then power line resistance decreases, but manufacturing complexity increases
Solution Approach 1:
Different metal layers are assigned different thicknesses based on their specific functional requirements. The first metal layer has a first thickness optimized for signal routing, the second metal layer has a second thickness (greater than first) optimized for power delivery where lower resistance is critical, and the third metal layer has a third thickness optimized for its specific routing needs. This local differentiation of thickness quality allows resistance optimization where needed without uniformly increasing manufacturing complexity across all layers.
Solution Approach 2:
The patent systematically varies the thickness parameter of metal layers across the interconnection structure. By changing the thickness parameter from layer to layer (first thickness < second thickness, with third thickness varying), the electrical resistance parameter is directly controlled. Thicker layers provide lower resistance paths for power lines, while thinner layers provide finer routing precision for signal lines.
3Quantity of substance
If metal layers are stacked closely to increase density, then routing density increases, but intra-cell coupling capacitance increases
Solution Approach 1:
By utilizing the vertical dimension with multiple stacked metal layers, the patent achieves high routing density without requiring metal layers to be placed in close horizontal proximity. The vertical separation between layers, combined with optimized pitch dimensions, allows dense routing capacity while maintaining sufficient electrical isolation to control coupling capacitance between adjacent layers.
Solution Approach 2:
The pitch parameter is locally optimized for each metal layer based on its specific routing density requirements and coupling capacitance constraints. The first metal layer has a first pitch, the second metal layer has a second pitch, and the third metal layer has a third pitch, with each pitch value tailored to balance routing density against coupling capacitance for that specific layer's function.
Data Source
AI summary
A semiconductor device includes a substrate having a first active region disposed in a first region of a substrate and a second active region disposed in a second region of the substrate. A first gate stack is disposed over the first active region and a second gate stack is disposed over the second active region, the first and second gate stacks having elongated shapes oriented in a first direction. A first metal layer is disposed over the first gate stack and the second gate stack. The first metal layer includes first metal layer structures oriented in a second direction orthogonal to the first direction. A second metal layer disposed over the first metal layer. The second metal layer includes second metal layer structures oriented in the first direction. A third metal layer is disposed over the second metal layer. The third metal layer includes a third metal layer structures oriented in the second direction.