Semiconductor Interconnect Etching via Dual Mask Layers
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to achieve precise etching in the side wall process without damaging the insulating layer, as existing methods struggle to selectively remove metal interconnects without etching the surrounding insulating material, which is crucial for maintaining high integration density and electrical isolation.
Innovation Solution
A method involving the formation of a first and second mask layer, where the second mask layer has openings over the first interconnect, allowing selective removal of the first interconnect while protecting the insulating layer, using a carbon-based first mask layer with a slower etching rate and anisotropic RIE to create loop-shaped interconnects and bit lines without damaging the insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to remove metal interconnects, then the metal layer can be removed, but the insulating layer is also damaged due to lack of selectivity
Solution Approach 1:
A mask layer is introduced as an intermediary substance between the etching tool and the metal interconnect. This mask layer selectively protects the insulating layer while allowing controlled removal of the metal layer, thereby resolving the selectivity issue in the etching process
Solution Approach 2:
The etching parameters are changed by applying different etching conditions to different regions. The mask layer creates a parameter difference where the etching rate is high for metal in exposed regions and zero for metal under the mask, while the insulating layer is protected throughout
2Reliability
If the etching is extended to remove all metal to ensure complete interconnect formation, then interconnect completeness is improved, but the insulating layer suffers from over-etching damage
Solution Approach 1:
The mask layer is applied in advance before the etching process to pre-determine the boundaries of metal removal. This preliminary protective action ensures that etching stops exactly where needed without extending into the insulating layer, preventing over-etching while ensuring complete interconnect formation
3Productivity
If the integration degree is increased to improve device functionality, then device capability is enhanced, but interconnect spacing becomes narrower requiring higher etching precision
Solution Approach 1:
The mask layer serves as a precise intermediary that defines narrow interconnect spacing with high accuracy. By controlling the mask layer dimensions and positioning, the etching process can achieve the required precision for narrow spacings enabled by high integration degree
Solution Approach 2:
The mask layer provides local quality control by having different properties in different regions - it is present in some areas to protect the insulating layer and absent in other areas to allow metal removal. This local differentiation enables precise control of interconnect spacing at high integration densities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise formation of interconnects and bit lines with loop configurations, ensuring electrical connectivity while minimizing etching of the insulating layer, thus enhancing the precision and reliability of semiconductor device manufacturing.
Implementation Method 1
using a carbon-based first mask layer with a slower etching rate and anisotropic RIE to create loop-shaped interconnects
Implementation Method 2
using a carbon-based first mask layer with a slower etching rate
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming an insulating layer on a semiconductor layer; forming a metal layer on the insulating layer; and forming a first interconnect by selectively etching the metal layer. The first interconnect is electrically connected to the semiconductor layer and has a loop configuration. The method includes forming a first mask layer covering the first interconnect and the insulating layer; and forming a second mask layer on the first mask layer. The second mask layer has a first opening over a portion of the first interconnect. The method further includes exposing the portion of the first interconnect by selectively removing the first mask layer using the second mask layer; and forming a second interconnect by selectively removing the portion of the first interconnect using the first mask layer. The second interconnect has two ends and is electrically connected to the semiconductor layer.