Group III-V Semiconductor Interconnect Height via Photoresist Undercut
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Solution Overview
Problem
Metal interconnects used in general power devices are inadequate for high-frequency power devices due to insufficient height, leading to increased parasitic impedance and performance issues when operating under high voltage, high current, and high frequency conditions.
Innovation Solution
A process for making an interconnect for group III-V semiconductor devices involves applying a positive photoresist layer and an image-reversible photoresist layer, subjecting them to patternwise and flood exposure, and then developing to create undercut sidewalls, followed by depositing a diffusion barrier and copper layers to form an interconnect with increased height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If metal interconnects with conventional thickness (2 μm) are used for general power devices, then the manufacturing process is simple, but the interconnect height is insufficient for high-frequency power devices, leading to increased parasitic impedance and degraded performance
Solution Approach 1:
The patent applies preliminary action by forming an undercut structure in the photoresist layer before depositing the metal interconnect. This undercut structure is created through a multi-step photoresist processing sequence (patternwise exposure, image reversal bake, flood exposure) that prepares the mold in advance to receive and shape the metal deposit, ensuring the interconnect achieves the required height without requiring complex subsequent processing steps.
Solution Approach 2:
The patent employs dimensionality change by transitioning from a planar photoresist structure to a three-dimensional undercut structure. The photoresist is transformed from a flat layer into a mold with sidewalls that extend laterally outward, creating a vertical cavity space. This dimensional transformation enables the metal interconnect to be deposited with significantly increased height while maintaining control over its shape and dimensions.
2Speed
If the operating frequency of high-frequency power devices is increased, then the device performance improves, but the parasitic impedance increases significantly, negatively affecting operating performance
Solution Approach 1:
The patent applies parameter changes by fundamentally altering the geometric parameters of the interconnect, specifically increasing its height from conventional thickness (2 μm) to significantly greater heights (e.g., 5 μm, 10 μm, or more). This parameter change directly reduces the parasitic impedance of the device, enabling it to maintain good operating performance even at high frequencies where parasitic effects would otherwise be significant.
3Reliability
If a stacked-layer structure with multiple adhesion layers and diffusion barrier layers is formed, then the adhesion and diffusion prevention are improved, but the process complexity and manufacturing steps increase
Solution Approach 1:
The patent uses the photoresist layer as an intermediary tool to create the undercut structure that facilitates metal deposition. Rather than relying solely on complex stacked-layer adhesion structures, the photoresist intermediary is shaped into an undercut mold that physically guides and contains the metal deposit, ensuring proper adhesion and shape control. The photoresist is then removed, leaving the formed interconnect structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process results in an interconnect with significantly increased height, enhancing electric conductivity and heat dissipation, suitable for high-frequency power devices, thereby improving their operating performance.
Implementation Method 1
subjecting the image-reversible photoresist layer and the positive photoresist layer to patternwise exposure so as to permit each of the image-reversible photoresist layer and the positive photoresist layer to be formed into a first portion which is in a developable form and a second portion which is in a non-developable form
Implementation Method 2
subjecting the image-reversible photoresist layer to image reversal bake so as to convert the first portion and the second portion of the image-reversible photoresist layer from the developable form and the non-developable form into the non-developable form and the developable form, respectively
Implementation Method 3
depositing a diffusion barrier and copper layers to form an interconnect with increased height
Data Source
AI summary
A process for making an interconnect of a group III-V semiconductor device includes the steps of applying a positive photoresist layer and an image-reversible photoresist layer, subjecting the image-reversible photoresist and positive photoresist layers to patternwise exposure, subjecting the image-reversible photoresist layer to image reversal bake, subjecting the image-reversible photoresist and positive photoresist layers to flood exposure, subjecting the image-reversible photoresist and positive photoresist layers to development, depositing a diffusion barrier layer, depositing a copper layer, and removing the image-reversible photoresist and positive photoresist layers.