Semiconductor Device Interconnect Inductance Reduction
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Solution Overview
Problem
The pad-on element structure for nitride semiconductor devices faces challenges in reducing interconnect inductance, particularly when extracting electric current, as it can lead to increased resistance and potential interconnect fusion due to current concentration and intersecting paths during flip-chip mounting.
Innovation Solution
A semiconductor device configuration with a half-bridge structure formed on a common substrate using first and second common interconnects that intersect, allowing for shorter interconnects, reduced resistance, and low inductance, along with a grid pattern of interconnects and insulating films to facilitate efficient current extraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If pad-on element structure is used for miniaturization, then chip area is reduced, but interconnect inductance cannot be sufficiently reduced
Solution Approach 1:
The patent transitions from planar pad-on-element interconnects to three-dimensional vertical vias and stacked interconnect layers. By utilizing the vertical dimension with multiple interconnect layers (first common interconnects, second common interconnects, third common interconnects) stacked above each other, the patent achieves shorter current paths and reduced inductance while maintaining the compact chip area of the pad-on-element structure.
2Ease of operation
If interconnects are extended to extract current from pads, then current extraction is achieved, but interconnect resistance and inductance increase
Solution Approach 1:
The patent divides the current extraction path into multiple segmented interconnect layers rather than using a single long interconnect. The first common interconnects connect to first drain pads, second common interconnects connect to second drain pads, and third common interconnects provide additional extraction paths. This segmentation creates multiple shorter current paths, reducing overall resistance and inductance while achieving effective current extraction.
Solution Approach 2:
The patent utilizes vertical stacking of interconnect layers to create three-dimensional current extraction paths. By arranging interconnects in multiple layers above the semiconductor layer, the patent shortens the horizontal distance current must travel while providing multiple parallel extraction paths, thereby reducing both resistance and inductance.
3Area of stationary object
If flip-chip mounting is used for miniaturization, then footprint is reduced, but current extraction paths may intersect causing resistance increase
Solution Approach 1:
The patent resolves path intersections by transitioning from two-dimensional planar routing to three-dimensional vertical stacking. Interconnects that would intersect in the planar view are separated in the vertical dimension across multiple layers, allowing current to flow through non-intersecting paths while maintaining the compact footprint required for flip-chip mounting.
Data Source
AI summary
A semiconductor device includes: a high-side transistor having a first gate electrode, first drain electrodes and first source electrodes; a low-side transistor having a second gate electrode, second drain electrodes and second source electrodes; a plurality of first drain pads that are disposed above the first drain electrodes and are electrically connected to the first drain electrodes; a plurality of first source pads that are disposed above the second source electrodes and are electrically connected to the second source electrodes; a plurality of first common interconnects that are disposed above the first source electrodes and above the second drain electrodes and are electrically connected to the first source electrodes and the second drain electrodes; and a plurality of second common interconnects that are connected to the first common interconnects, and extend in a direction that intersects with the first common interconnects.