Semiconductor Interconnect Layout Without Redundant Metal Layers
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving compact and efficient interconnect structures that optimize performance and reduce power consumption, particularly in static random access memory (SRAM) devices, due to redundant metallization layers and redistribution layers that are not necessary for the main function.
Innovation Solution
The formation of a semiconductor device with a simplified interconnect structure that eliminates redundant metallization layers and redistribution layers, utilizing a minimum number of stacked conductive wirings and vias, and incorporating a direct bonding process for conductive patterns to enhance performance and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If redundant metallization layers and redistribution layers are included in the interconnect structure, then the device can be manufactured using conventional processes, but the device complexity and power consumption increase
Solution Approach 1:
The patent extracts and removes redundant metallization layers and redistribution layers from the interconnect structure. The bonding patterns are formed in direct contact with the conductive patterns, eliminating the need for intermediate redistribution layers. This extraction of unnecessary components reduces device complexity while maintaining manufacturability through direct bonding processes.
2Ease of manufacture
If redundant metallization layers and redistribution layers are included in the interconnect structure, then the device can be manufactured using conventional processes, but the power consumption increases
Solution Approach 1:
The patent extracts and removes redundant metallization layers and redistribution layers from the interconnect structure. The bonding patterns are formed in direct contact with the conductive patterns, eliminating the need for intermediate redistribution layers. This extraction of unnecessary components reduces device complexity while maintaining manufacturability through direct bonding processes.
3Productivity
If a simplified interconnect structure with minimum stacked conductive wirings is used, then the operational rate improves and power consumption reduces, but the manufacturing process becomes more complex
Solution Approach 1:
The patent merges the bonding pattern formation process with the interconnect structure fabrication. The bonding patterns are formed in direct contact with the conductive patterns through integration of the interconnect structure, eliminating the need for separate redistribution layers. This merging of functions reduces the number of discrete components while maintaining manufacturability through coordinated processing steps.
4Productivity
If a simplified interconnect structure with minimum stacked conductive wirings is used, then the operational rate improves and power consumption reduces, but the manufacturing process becomes more complex
Solution Approach 1:
The patent merges the bonding pattern formation process with the interconnect structure fabrication. The bonding patterns are formed in direct contact with the conductive patterns through integration of the interconnect structure, eliminating the need for separate redistribution layers. This merging of functions reduces the number of discrete components while maintaining manufacturability through coordinated processing steps.
Data Source
AI summary
A semiconductor device includes a first die. The first die includes a first interconnect structure and a plurality of first bonding patterns, wherein the first interconnect structure comprises a plurality of first conductive vias and a plurality of first conductive wirings in direct contact with the first conductive vias and the first bonding patterns, the first conductive vias are irregularly arranged, and the first bonding patterns are irregularly arranged.