Semiconductor Interconnect Layout for Scaled MOSFET Reliability
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Solution Overview
Problem
The scaling down of MOSFETs in semiconductor devices leads to deterioration in operational properties, necessitating improvements in electrical characteristics and reliability.
Innovation Solution
The semiconductor device incorporates specific interconnection line configurations and fabrication methods, including alternating open lines and metal layers with defined distances and protrusions, to enhance electrical performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled down to meet increasing demand for smaller pattern sizes, then device density and integration are improved, but operational properties and electrical characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D interconnection to 3D stacked metal layers, allowing interconnection lines to extend vertically across multiple logic cells. This dimensional change enables shorter horizontal distances (12-18 nm) between opposing interconnection lines while maintaining overall device area, thereby improving electrical characteristics without further scaling down the pattern size.
Solution Approach 2:
The interconnection structure is segmented into multiple metal layers with distinct functions. The first metal layer contains right-sided interconnection lines (first, second, third right interconnection lines) while the second metal layer contains left-sided interconnection lines. This segmentation allows independent optimization of each layer's routing and spacing, improving overall electrical performance.
2Length of stationary object
If interconnection lines are positioned closer together to reduce distance, then electrical resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
By utilizing vertical stacking of metal layers, the patent achieves short effective distances (12-18 nm) between opposing interconnection lines in the horizontal direction while maintaining adequate vertical separation. This 3D arrangement reduces the critical dimension requirements for manufacturing compared to achieving the same distance in a single planar layer.
Solution Approach 2:
The patent introduces interlayer insulating layers between the first and second metal layers as intermediary structures. These insulating layers provide physical separation and alignment references, enabling precise positioning of interconnection lines at 12-18 nm distances while maintaining manufacturability through standardized layer spacing.
3Reliability
If more metal layers and interconnection lines are added to improve electrical characteristics, then device complexity increases
Solution Approach 1:
The patent segments the interconnection function into two dedicated metal layers: the first metal layer for right-sided interconnection lines and the second metal layer for left-sided interconnection lines. This functional segmentation improves electrical characteristics by providing optimized routing paths while keeping the overall structure manageable through clear functional division.
Solution Approach 2:
Each metal layer serves multiple functions simultaneously: providing electrical interconnection, establishing alignment references for subsequent layers, and creating insulated separation between opposing conductors. This multi-functionality reduces the need for additional dedicated structures, thereby limiting the increase in device complexity.
Data Source
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AI summary
A semiconductor device may include first and second logic cells, which are on a substrate and are spaced apart from each other in a first direction, and each of which includes PMOSFET and NMOSFET regions, and first and second metal layers on the first and second logic cells, respectively. The first metal layer may include first, second, and third right interconnection lines, which extend in the first direction parallel to each other, with the second right interconnection line between the first and third right interconnection lines. The second metal layer may include a first left interconnection line. A shortest distance between the first right interconnection line and the first left interconnection line in the first direction may be defined as a first distance that is in a range from 12 nm to 18 nm.