Semiconductor Interconnect Pattern Layout for Contact Pad Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In NAND flash memory semiconductor devices, the resolution of patterns at the boundary regions of memory cell units is lower than in the central regions, and the miniaturization of core circuit units leads to difficulties in pattern formation due to reduced lithography margins, especially when forming contact pads that disrupt periodicity, resulting in a limited number of interconnect lines that can be arranged around the pads.
Innovation Solution
A semiconductor device with a pattern layout that includes a first interconnect pattern and a contact pad, where the contact pad has a width triple the predetermined pitch, and an auxiliary pattern is used to maintain periodicity, allowing for improved lithography margins and increased flexibility in design by enabling more interconnect lines to be arranged around the contact pad.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a contact pad with width several-fold of pattern pitch is provided in L&S periodic pattern, then electrical connection capability is improved, but large space must be assured between interconnect line and contact pad based on MSR restrictions, reducing the number of interconnect lines that can be arranged
Solution Approach 1:
The contact pad structure is segmented into multiple regions with different width characteristics. The contact pad includes a first region with width equal to the pitch and a second region with width several-fold the pitch, allowing different portions to serve different functions while maintaining compliance with MSR restrictions in critical areas.
Solution Approach 2:
Different regions of the contact pad are designed with different width characteristics to fulfill different requirements. The first region maintains pitch-width for MSR compliance, while the second region provides expanded width for improved electrical connection capability, applying local quality differentiation to resolve the contradiction.
2Manufacturing precision
If auxiliary pattern is arranged on mask to maintain periodicity, then lithography margin is improved, but device complexity increases due to additional pattern elements
Solution Approach 1:
The auxiliary pattern is extracted as a separate, dedicated component in the mask design, distinct from the primary interconnect and contact pad patterns. This extraction allows the auxiliary pattern to be optimized specifically for maintaining periodicity and improving lithography margins without complicating the functional design of the interconnect structure.
Solution Approach 2:
The auxiliary pattern serves multiple functions: it maintains periodicity in the L&S pattern, improves lithography margins, and enables better focus depth and exposure latitude. This multi-functionality justifies the additional complexity by delivering multiple benefits from a single pattern element.
3Area of moving object
If pattern size is reduced for miniaturization, then integration density is improved, but lithography margin is reduced making pattern formation difficult
Solution Approach 1:
The invention utilizes periodic L&S patterns with carefully controlled pitch dimensions. By maintaining periodicity through auxiliary patterns and designing the contact pad width relationship to the pitch (width = pitch × n), the system achieves miniaturization while preserving lithography margins through the periodic structure's inherent robustness.
Solution Approach 2:
The invention changes the parameter relationship between contact pad width and pattern pitch, defining contact pad width as an integer multiple of the pitch. This parameter change allows systematic scaling while maintaining lithography margins, as the auxiliary patterns can be proportionally adjusted to maintain periodicity regardless of absolute size.
Data Source
AI summary
According to one embodiment, a semiconductor device having a pattern layout includes a first interconnect pattern and a contact pad. The first interconnect pattern includes lines and spaces which are alternately aligned in a first direction with a predetermined pitch. The contact pad is arranged between the lines in the first interconnect pattern and has a width that is triple the predetermined pitch. An interval between the line in the first interconnect pattern and the contact pad is the predetermined pitch, and the predetermined pitch is 100 nm or below.