Semiconductor Local Interconnect Fabrication via Non-Functional Pattern Removal
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Solution Overview
Problem
The existing semiconductor device fabrication processes face challenges in achieving design flexibility and reliability due to non-functional local interconnects, which increase net capacitance and degrade device performance, requiring additional patterning operations that elevate manufacturing costs.
Innovation Solution
A novel manufacturing operation is introduced to form local interconnects by identifying and removing non-functional patterns, using a method that involves preparing initial and cutting patterns, identifying non-functional connections, and forming a photo mask to pattern and fill openings with conductive material, ensuring only functional interconnects are formed between source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If local interconnects are formed to connect source/drain regions, then design flexibility and electrical connection height are improved, but non-functional local interconnects increase net capacitance and degrade device performance
Solution Approach 1:
The patent applies preliminary action by identifying and removing non-functional local interconnect patterns before they are formed through the complete fabrication process. The method prepares initial connection patterns, identifies non-functional ones, prepares cutting patterns to remove them, and then forms only the functional local interconnects, preventing capacitance increase from the outset
Solution Approach 2:
The patent applies the extraction principle by specifically removing non-functional local interconnect patterns from the design. The method identifies patterns that do not connect source/drain regions and eliminates them through cutting patterns, extracting only the harmful elements while preserving functional interconnects
2Reliability
If non-functional local interconnect patterns are removed, then capacitance is reduced and device performance is improved, but additional patterning operations are required increasing manufacturing complexity
Solution Approach 1:
The patent applies merging by combining the identification of non-functional patterns with the preparation of cutting patterns in an integrated workflow. The method merges pattern recognition, design modification, and fabrication preparation into a unified process that eliminates redundant steps
Solution Approach 2:
The patent applies self-service by enabling the design process to automatically identify and mark non-functional local interconnect patterns for removal. The system uses the initial connection patterns themselves to generate cutting patterns, allowing the design to self-correct without external intervention
3Manufacturing precision
If additional patterning operations are performed to remove non-functional interconnects, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent applies preliminary action by preparing cutting patterns in advance that precisely define where non-functional interconnects should be removed. This preliminary preparation ensures high manufacturing precision by providing clear guidance for the patterning operations before actual fabrication begins
Solution Approach 2:
The patent applies parameter changes by modifying the connection patterns through systematic changes in pattern configuration. The method transforms initial connection patterns into final patterns by applying specific transformation rules that identify non-functional elements, enabling precise control over which interconnects are formed or removed
Data Source
AI summary
In a method of manufacturing a semiconductor device, initial connection patterns are prepared, initial cutting patterns for cutting the initial connection patterns are prepared, non-functional connection patterns at least from the initial connection patterns are identified, final cutting patterns are prepared from the initial cutting patterns and the non-functional connection patterns, a photo mask is prepared from the final cutting patterns, a photo resist pattern is formed over a target layer by a lithography operation using the photo mask, the target layer is patterned to form openings in the target layer by using the photo resist pattern, and connection layers are formed by filling the openings with a conductive material.