Semiconductor Interconnect Structure with Penetrating Conductive Features
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Solution Overview
Problem
Current methods for manufacturing interconnect structures in semiconductor devices face challenges with high aspect ratio trenches, resulting in reduced metal coverage, discontinuous configurations, and increased resistance, which affect the reliability and performance of the circuits.
Innovation Solution
A semiconductor device structure featuring a diffusion barrier layer, passivation layer, and conductive features with insulative liners and voids, where the conductive features penetrate through the passivation layer and contact the diffusion barrier layer, and a manufacturing method involving deposition, patterning, and double exposure techniques to form conductive features with high aspect ratios and continuous configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If conventional methods are used to manufacture interconnect structures with high aspect ratio trenches, then the trench depth can be increased, but metal coverage is reduced and the configuration becomes discontinuous
Solution Approach 1:
The conductive layer is divided into multiple segments corresponding to different trenches, with each segment independently patterned and deposited. This segmentation allows for better control of metal deposition in each individual trench, ensuring continuous coverage even in high aspect ratio structures where conventional blanket deposition would fail.
Solution Approach 2:
The conductive layer is deposited and patterned before the passivation layer is formed. This preliminary action ensures that the conductive features are already in place and continuous before the passivation process, preventing any discontinuities that might occur during subsequent processing steps.
2Ease of manufacture
If conventional interconnect structures are used, then the manufacturing process is simpler, but resistance is increased and signal transmission speed is reduced
Solution Approach 1:
The conductive layer is selectively deposited and patterned in specific locations corresponding to individual trenches, creating locally optimized conductive paths. This local quality approach ensures that each conductive feature has the optimal geometry and continuity for low resistance, while the overall manufacturing process remains manageable through systematic repetition.
Solution Approach 2:
The conductive features are designed with vertical continuity through the passivation layer, adding a dimensional aspect to the interconnect structure. This vertical dimension allows for direct connection between upper and lower metal wirings, reducing the number of intermediate vias and improving signal transmission speed.
3Speed
If the conductive features are made thinner to reduce capacitance, then signal transmission speed improves, but manufacturing precision requirements increase
Solution Approach 1:
The conductive layer is patterned using the target pattern as a mask, where the target pattern itself defines the precise geometry of the conductive features. This self-service approach allows the pattern definition process to automatically control the thickness and dimensions of the conductive features, reducing the need for separate precision control steps.
Solution Approach 2:
The thickness and dimensions of the conductive features are controlled by adjusting parameters of the deposition and patterning processes, such as deposition rate, pattern density, and etch conditions. These parameter changes allow for precise control of conductive feature geometry to achieve the desired thin profile for low capacitance while maintaining manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution increases the density and reliability of conductive features, reducing resistance and improving signal transmission speed by optimizing the interconnect structure and manufacturing process.
Implementation Method 1
a diffusion barrier layer disposed on the substrate
Implementation Method 2
a passivation layer disposed on the diffusion barrier layer
Data Source
AI summary
The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, a diffusion barrier layer, a passivation layer, and a plurality of conductive features. The diffusion barrier layer is disposed on the substrate, and the passivation layer is disposed on the diffusion barrier layer. The conductive features penetrate through the passivation layer and contact the diffusion barrier layer.