Void-Free Semiconductor Interconnect Pillars for High-Aspect Vias
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Solution Overview
Problem
Conventional processes for manufacturing interconnect structures in semiconductor devices face challenges in filling large aspect ratio trenches and vias with conductive layers, leading to voids and unreliable connections due to the difficulty of electrochemical plating processes.
Innovation Solution
A method involving the formation of three metal layers, followed by etching operations to create metal pillars, ensuring no voids are generated, and the use of specific materials and processes such as plasma enhanced chemical vapor deposition and ion beam etching to form interconnect structures with vertically aligned sidewalls and cap layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrochemical plating is used to fill trenches and vias, then conductive layers can be deposited, but voids form and connections become unreliable due to large aspect ratios
Solution Approach 1:
The patent divides the interconnect structure into multiple metal layers (first metal layer, second metal layer, third metal layer) separated by dielectric layers. This segmentation allows each layer to be formed with smaller aspect ratios, enabling complete filling without voids while maintaining reliable connections. The etching operations create metal pillars that extend through multiple dielectric layers, ensuring continuous conductive paths.
Solution Approach 2:
The patent transitions from planar interconnect structures to three-dimensional metal pillar structures. By forming vertical metal pillars that extend through multiple dielectric layers, the design moves from two-dimensional routing to three-dimensional architecture, allowing better control over aspect ratios and eliminating void formation in the conductive paths.
2Productivity
If device scaling continues, then circuit density increases, but conventional manufacturing processes become insufficient for filling large aspect ratio structures
Solution Approach 1:
The patent segments the interconnect system into multiple discrete metal layers and dielectric layers. This segmentation reduces the aspect ratio of individual trenches and vias that need to be filled, making them manufacturable with conventional electrochemical plating processes while still achieving high circuit density through vertical stacking.
Solution Approach 2:
The patent performs preliminary etching operations to create metal pillars and openings in dielectric layers before depositing conductive materials. This preliminary structuring ensures that subsequent plating operations work with optimized aspect ratios, making the manufacturing process feasible for scaled devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents the formation of voids in interconnects, enhancing the reliability of semiconductor devices by ensuring continuous, seamless conductive paths without gaps, thereby improving the integrity of metal interconnects in advanced semiconductor manufacturing.
Implementation Method 1
a plasma enhanced chemical vapor deposition process, a chemical vapor deposition process
Implementation Method 2
an ion beam etching process
Data Source
AI summary
An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.