Semiconductor Interconnects Using Pre-formed Conductive Wires
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Solution Overview
Problem
Conventional interconnects in semiconductor assemblies face challenges such as non-uniform metallization, high aspect ratio via formation difficulties, air trapping, and increased processing time and cost, leading to inconsistent electrical connections and compromised integrity.
Innovation Solution
The use of pre-formed conductive wires or stud bumps to directly connect bond-sites before encapsulation, eliminating the need for via formation, plating, and filling, and simplifying the manufacturing process while ensuring uniform and robust electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via formation and filling processes are used to create interconnects, then electrical connections can be established between semiconductor devices, but the metallization becomes non-uniform and the interconnect integrity is compromised
Solution Approach 1:
The patent applies preliminary action by pre-forming conductive structures (such as conductive posts or bumps) on the semiconductor device before packaging. This eliminates the need for subsequent via drilling and metallization deposition, ensuring uniform conductive material distribution and avoiding the non-uniform metallization problems associated with conventional via filling processes.
2Reliability
If high aspect ratio vias are formed to connect stacked packages, then electrical interconnects between packages can be established, but the via formation becomes difficult and air trapping occurs
Solution Approach 1:
The patent forms conductive structures preliminarily on the device surface before stacking, eliminating the need to drill high aspect ratio vias through the package and device later. This preliminary formation of conductive posts or bumps avoids the manufacturing difficulties and air trapping issues associated with high aspect ratio via formation.
Solution Approach 2:
Instead of forming vias through the package substrate after stacking (conventional approach), the patent inverts the sequence by forming conductive structures on the device surface before packaging. This reversal of the process sequence eliminates the high aspect ratio via formation problem entirely.
3Reliability
If conventional interconnect formation processes are used, then electrical connections can be made, but the processing time and manufacturing cost increase
Solution Approach 1:
The patent performs interconnect formation preliminarily during device fabrication by creating conductive posts or bumps on the device surface before packaging. This eliminates the need for separate via drilling, cleaning, metallization deposition, and filling steps, significantly reducing processing time and manufacturing cost while maintaining connection quality.
Data Source
AI summary
Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.