Semiconductor Interconnect with Dual-Layer Resistance Compensation
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Solution Overview
Problem
Multi-finger structures in semiconductor devices experience non-uniform current distribution due to varying resistance paths, limiting the current carrying capacity, especially when interconnect fingers have a pyramidal shape with wider bases and narrower ends.
Innovation Solution
A semiconductor device with two interconnect layers is proposed, where the top layer has interweaved fingers varying in width and the bottom layer is arranged to compensate for the resistance differences in the top layer, ensuring all current paths have equal resistance through varying strip widths or resistivity, maximizing current capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If pyramidal shaped interconnect fingers are used (wide at base, narrow at end), then current density at the base is reduced, but current distribution becomes non-uniform with lower resistance paths through the middle
Solution Approach 1:
The patent transitions from a single-layer pyramidal finger structure to a two-layer interconnect structure. The first layer contains the pyramidal fingers, while the second layer introduces additional current paths that run parallel to and compensate for the non-uniform resistance distribution in the first layer, effectively adding a dimensional solution to a two-dimensional problem.
Solution Approach 2:
The patent modifies the resistance parameter distribution by varying the width of interconnect fingers in the second layer. Specifically, the outer fingers in the second layer are made wider than inner fingers, creating lower resistance paths that compensate for the higher resistance in corresponding paths of the first layer, thereby achieving uniform total resistance across all current paths.
2Reliability
If equal width interconnect fingers are used, then current distribution is uniform, but total current capacity is limited by the base current density
Solution Approach 1:
The patent combines two separate interconnect layers with different resistance characteristics into a single functional system. The first layer provides uniform current distribution with equal width fingers, while the second layer with varying widths compensates for resistance differences, and their combined effect achieves both uniform current distribution and enhanced current capacity.
Solution Approach 2:
The patent creates a composite interconnect structure where two layers with different geometric configurations (equal width and varying width fingers) are stacked together. This composite structure leverages the advantages of both configurations: the uniformity of equal width fingers and the current capacity enhancement of varying width fingers, achieving superior overall performance.
3Productivity
If two layers with varying finger widths are used, then current capacity increases, but device complexity increases
Solution Approach 1:
The patent segments the interconnect function into two distinct layers, each with specific optimization goals. The first layer focuses on uniform current distribution with equal width fingers, while the second layer focuses on resistance compensation with varying widths. This segmentation allows independent optimization of each layer while maintaining overall system performance.
Data Source
AI summary
A semiconductor device including an interconnect. The interconnect is arranged to transfer current from one terminal to another, and the interconnect includes a first layer including a plurality of interweaved fingers, and each of the interweaved fingers varies in width in a direction of propagation current thereby resulting in a difference of resistance within each of the interweaved fingers in the direction of propagation of current; a second layer arranged below the first layer. The second layer compensates for the difference of resistance in the first layer.