3D Stacked Semiconductor Interconnect Structure
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Solution Overview
Problem
Current semiconductor assembly technologies face challenges in achieving efficient 3D integration of stacked circuits with different fabrication processes, which hinders performance enhancement, density increase, and cost reduction.
Innovation Solution
A semiconductor assembly is manufactured by stacking a second device on a first device with a cap dielectric layer and an interconnect structure, including legs and a cross member, and bonding layers to establish electrical connections between conductive features, allowing for efficient electrical connectivity and bonding between the devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stacked 3D integrated circuits are implemented to increase performance and density, then performance and density are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The interconnect structure is segmented into multiple functional components: legs that penetrate through the cap dielectric layer and bonding layers, cross members that provide lateral connections, and bonding layers that enable device attachment. This segmentation allows each component to be optimized independently for its specific function while contributing to the overall 3D integration performance.
Solution Approach 2:
The patent transitions from planar 2D circuit layouts to three-dimensional stacked architecture. Conductive features are positioned at different vertical levels (first conductive feature in the first device, second conductive feature in the second device), and interconnected through vertical legs and horizontal cross members, creating a multi-dimensional interconnect network that increases density without proportionally increasing manufacturing complexity.
2Adaptability or versatility
If chips fabricated using different fabrication processes are stacked, then versatility and integration options increase, but manufacturing precision and reliability challenges increase
Solution Approach 1:
The bonding layers serve multiple functions: they provide mechanical attachment between devices fabricated using different processes, establish electrical connections between conductive features, and offer a standardized interface that can accommodate various device types and fabrication methodologies. This multi-functionality enables versatile integration while maintaining consistent manufacturing requirements.
Solution Approach 2:
The bonding layers act as intermediary elements between devices from different fabrication processes. These layers provide a standardized bonding interface that mediates the connection between disparate devices, allowing precise alignment and reliable electrical contact while accommodating variations in device geometry and conductive feature positioning.
3Reliability
If interconnect structures with legs penetrating through cap dielectric layer are used, then electrical connectivity between stacked devices is improved, but manufacturing complexity and process steps increase
Solution Approach 1:
The interconnect structure merges multiple functions into a unified design: legs simultaneously provide mechanical support and electrical conduction pathways, cross members integrate multiple leg connections into a cohesive network, and the entire structure is embedded within the cap dielectric layer which provides both electrical isolation and structural support. This merging reduces the number of separate components and simplifies manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective electrical connectivity and bonding between stacked devices, enhancing performance and density while reducing costs by allowing for the integration of chips fabricated using different processes.
Implementation Method 1
fusing the first bonding layer and the second bonding layer
Data Source
AI summary
The present disclosure provides a semiconductor assembly. The semiconductor assembly includes a first device, a second device, and an interconnect structure configured to electrically coupled the first device and the second device. The second device is stacked on the first device. The interconnect structure includes a first leg, a second leg, and a cross member connecting the first leg to the second leg, wherein the first leg penetrates through the cap dielectric layer and the second device and contacts a first conductive feature of the first device, and a second leg penetrates through the cap dielectric layer and contacts a second conductive feature of the second device.