Semiconductor Interconnect Structure Using Stacked Mask Layer Etching
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming interconnect structures with contact vias of unequal depths in source/drain and gate regions, leading to complex processes and low production efficiency due to difficulties in etching and depositing conductive materials.
Innovation Solution
A method involving a stacked mask layer structure is used to form contact vias, where the first mask layer is used to expose the source/drain region and the second mask layer, with a different etching selectivity, is used to expose the gate structure, allowing for simultaneous formation of both contact vias with reduced process complexity and improved accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate mask layers are used for source/drain and gate contact vias, then etching selectivity is improved, but process complexity increases
Solution Approach 1:
The mask layer is divided into two distinct segments: a first mask layer for defining source/drain contact vias and a second mask layer for defining gate contact vias. This segmentation allows each mask layer to be optimized for its specific etching requirements, achieving different etching selectivities for different via types while maintaining clear process separation.
Solution Approach 2:
Different regions of the structure receive different mask layer configurations. The first mask layer is applied where source/drain contacts are needed, while the second mask layer is applied where gate contacts are needed. This local differentiation enables precise control over etching depth and selectivity in each region without affecting other areas.
2Adaptability or versatility
If contact vias of unequal depths are formed, then device functionality is improved, but etching and deposition difficulty increases
Solution Approach 1:
The etching process is segmented into separate operations for source/drain vias and gate vias. The first etching process forms source/drain contact vias to a first depth, while the second etching process forms gate contact vias to a second depth. This segmentation allows each etching operation to be independently optimized for its specific depth requirement, making unequal depth formation manageable.
Solution Approach 2:
The first mask layer is formed and used to define source/drain contact vias before the second mask layer is formed for gate contact vias. This preliminary action establishes the deeper vias first, then the shallower vias are formed subsequently, allowing the process to accommodate unequal depths through sequential operations rather than attempting to form all vias simultaneously.
3Productivity
If process steps are simplified, then production efficiency is improved, but contact via formation accuracy decreases
Solution Approach 1:
The contact via formation process is segmented into distinct steps with dedicated mask layers for source/drain and gate vias. This segmentation prevents confusion and errors that would arise from using a single mask layer for both via types, thereby maintaining high formation accuracy while keeping the process organized and efficient.
Solution Approach 2:
The first mask layer is formed preliminarily to define source/drain contact regions before the second mask layer is formed for gate contact regions. This preliminary definition ensures that subsequent etching and deposition steps are performed with precise spatial control, maintaining accuracy while enabling a systematic flow that improves overall process efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the process steps, enhances the accuracy of contact via formation, and improves the reliability and electrical properties of the interconnect structure by reducing the likelihood of position deviation and over-etching.
Implementation Method 1
the second mask layer, with a different etching selectivity, is used to expose the gate structure
Data Source
AI summary
Various embodiments provide semiconductor devices. A base including a substrate and an interlayer dielectric layer is provided. The base has a first region and a second region that have an overlapped third region. A mask layer having a stacked structure is formed on the interlayer dielectric layer at the overlapped third region. Using the mask layer as an etching mask, the interlayer dielectric layer at the first region at both sides of the mask layer is etched, to expose the substrate and form a first contact via at the first region. Using the mask layer as an etching mask, the interlayer dielectric layer at the second region at both sides of the mask layer is etched, to form a second contact via at the second region. A conductive layer is formed to fill the first contact via and the second contact via.