Semiconductor Interconnect Structure Using Segmented Sub-Vias
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Solution Overview
Problem
As semiconductor devices scale down, the shrinking size of vias and metal lines leads to fabrication challenges such as electrical open conditions and excessive resistance due to small interface areas, and enlarging vias can result in unintended electrical shorting.
Innovation Solution
The use of divided sub-vias, which are collectively used to electrically interconnect metal lines from different interconnect layers, allowing for improved connection areas and reduced resistance by maintaining a smaller thickness while enlarging the interface area through lateral offsetting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the via size is reduced to maintain scaling, then the device density increases, but the interface area becomes too small causing electrical open conditions and excessive resistance
Solution Approach 1:
The patent divides a single via into multiple sub-vias (first sub-via and second sub-via) that are laterally offset from each other. This segmentation allows each sub-via to have a sufficient interface area with the conductive lines while maintaining overall small via footprint for high device density. The multiple sub-vias collectively provide reliable electrical connection between interconnect layers.
2Reliability
If the via size is enlarged to improve connection area, then the interface area increases reducing resistance, but unintended electrical shorting occurs
Solution Approach 1:
By segmenting the via structure into multiple laterally offset sub-vias, each sub-via can be sized appropriately to provide sufficient connection area without being large enough to cause shorting to adjacent conductive lines. The lateral offset positioning ensures proper spacing and prevents harmful electrical shorting.
Solution Approach 2:
The patent applies different positioning (lateral offset) to different sub-vias, allowing each sub-via to be optimally positioned to maximize its interface area with the intended conductive line while maintaining safe distance from other conductive lines to prevent shorting.
3Ease of manufacture
If traditional single via structure is used, then the fabrication process is simpler, but alignment precision becomes increasingly difficult at nanometer nodes
Solution Approach 1:
The via is divided into multiple sub-vias with lateral offsets, which can be formed using standard photolithography and etching processes. The segmentation allows each sub-via to be more tolerant to alignment variations while collectively achieving the required connection, thereby maintaining fabrication simplicity while improving alignment precision at nanometer nodes.
Data Source
AI summary
The present disclosure provides an interconnect structure for a semiconductor device. The interconnect structure includes a first metal layer that contains a first metal line. The interconnect structure includes a dielectric layer located over the first metal layer. The dielectric layer contains a first sub-via electrically coupled to the first metal line and a second sub-via electrically coupled to the first sub-via. The second sub-via is different from the first sub-via. The interconnect structure includes a second metal layer located over the dielectric layer. The second metal layer contains a second metal line electrically coupled to the second sub-via. No other metal layer is located between the first metal layer and the second metal layer.