Semiconductor Interconnect Layout to Prevent TDDB Across Voltage Regions
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Solution Overview
Problem
The proximity of conductive layers in medium/high voltage device regions to low voltage device regions in semiconductor manufacturing leads to time-dependent dielectric breakdown, especially as process sizes shrink below 17 nm, affecting device quality.
Innovation Solution
Designing a semiconductor structure where the first conductive layer in the medium/high voltage region does not extend into the low voltage region, and a second conductive layer spans both regions, maintaining a safe distance to prevent dielectric breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the first conductive layer extends continuously across both medium/high voltage and low voltage device regions, then manufacturing simplicity is maintained, but time-dependent dielectric breakdown occurs due to insufficient spacing between conductive layers in different voltage regions
Solution Approach 1:
The first conductive layer is segmented into two distinct parts: a first portion in the medium/high voltage device region and a second portion in the low voltage device region. This segmentation creates sufficient spacing between conductive layers in different voltage regions, preventing time-dependent dielectric breakdown while maintaining manufacturing feasibility through controlled discontinuity.
Solution Approach 2:
Different spacing requirements are applied to different regions: the first conductive layer maintains closer spacing in the medium/high voltage region where it is necessary, while creating larger spacing in the low voltage region to prevent dielectric breakdown. This local differentiation of spacing quality resolves the contradiction between manufacturing simplicity and reliability.
2Manufacturing precision
If the spacing between conductive layers in medium/high voltage region is reduced to maintain manufacturing precision, then manufacturing precision is improved, but dielectric breakdown risk increases due to proximity to low voltage devices
Solution Approach 1:
By segmenting the first conductive layer into separate portions for medium/high voltage and low voltage regions, the invention allows optimized spacing in each region. The first portion can maintain precise alignment with smaller spacing for manufacturing precision, while the second portion maintains larger spacing to prevent dielectric breakdown, thus resolving the contradiction.
Solution Approach 2:
The invention applies different spacing qualities to different spatial locations: tighter spacing in the medium/high voltage region for manufacturing precision and larger spacing in the low voltage region for dielectric breakdown prevention. This local quality differentiation simultaneously achieves both manufacturing precision and harmful factor reduction.
Data Source
AI summary
The invention provides a semiconductor structure, which comprises a substrate, a first medium/high voltage device region and a low voltage device region are defined on the substrate, the first medium/high voltage device region comprises a first gate contact and a first source/drain contact, and the low voltage device region comprises two second source/drain contacts and a second gate contact, wherein the second gate contact is located between the two second source/drain contacts and directly contacts the two second source/drain contacts. A first conductive layer located in the first medium/high voltage device region, wherein the first conductive layer does not extend into the low voltage device region, and a second conductive layer located above the first conductive layer and spanning the first medium/high voltage device region and the low voltage device region.