Semiconductor Interconnect with Tungsten Landing Pads
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high-density integrated circuits with smaller feature sizes due to void formation in copper electroplating processes, which reduces manufacturing yields and reliability, especially as devices are scaled down.
Innovation Solution
The use of different materials for interconnect lines and landing pads, such as copper for low-resistance interconnects and tungsten for landing pads, which can be filled using CVD processes to prevent voids and allow for smaller feature sizes without compromising performance, along with optimized manufacturing methods to reduce contact resistance and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper electroplating is used to fill interconnect lines, then low resistance is achieved, but void formation occurs that reduces manufacturing yields and reliability
Solution Approach 1:
The patent applies different materials to different locations within the interconnect structure. Copper is used for interconnect lines where low resistance is critical, while tungsten is used for landing pads where void formation is problematic. This local differentiation resolves the contradiction by allowing copper electroplating in areas where it provides benefit while avoiding its harmful effects in areas prone to void formation.
Solution Approach 2:
The patent employs a composite interconnect structure combining copper and tungsten materials. The interconnect line is made of copper for optimal electrical performance, while the landing pad is made of tungsten to prevent void formation during electroplating. This composite approach allows the system to achieve both low resistance and high reliability simultaneously.
2Productivity
If feature sizes are reduced to achieve higher densities, then more devices fit on the die, but void formation increases and compromises reliability
Solution Approach 1:
The patent implements location-specific material selection where tungsten is used for landing pads in high-density areas prone to void formation, while copper is used for interconnect lines where electroplating can be controlled better. This allows the circuit to achieve high device density while maintaining reliability through targeted material placement.
3Reliability
If copper is used for interconnect lines, then low resistance is achieved, but void formation in landing pads reduces manufacturing yields
Solution Approach 1:
The patent applies different materials to different locations within the interconnect structure. Copper is used for interconnect lines where low resistance is critical, while tungsten is used for landing pads where void formation is problematic. This local differentiation resolves the contradiction by allowing copper electroplating in areas where it provides benefit while avoiding its harmful effects in areas prone to void formation.
Solution Approach 2:
The patent employs a composite interconnect structure combining copper and tungsten materials. The interconnect line is made of copper for optimal electrical performance, while the landing pad is made of tungsten to prevent void formation during electroplating. This composite approach allows the system to achieve both low resistance and high reliability simultaneously.
4Productivity
If standard cell area is reduced to achieve higher densities, then more functionality is achieved, but performance may be compromised
Solution Approach 1:
The patent implements location-specific material selection where tungsten is used for landing pads in high-density areas prone to void formation, while copper is used for interconnect lines where electroplating can be controlled better. This allows the circuit to achieve high device density while maintaining reliability through targeted material placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reduction of standard cell areas, maintains low resistance for interconnects, and minimizes void formation, enhancing manufacturing yields and reliability while achieving smaller feature sizes and higher densities in integrated circuits.
Implementation Method 1
copper electroplating processes
Implementation Method 2
tungsten for landing pads, which can be filled using CVD processes
Data Source
AI summary
One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.