Semiconductor Interconnects with Variable Line Widths and Air Gaps
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor device interconnect structures, electron migration at the junction of vias and conductive lines can lead to void formation and increased current density, which existing damascene methods struggle to prevent effectively.
Innovation Solution
The method involves forming conductive lines of varying widths, with wider lines at junctions to reduce electron migration and void formation, and optionally creating air gaps or voids adjacent to narrower lines for additional insulation, using techniques like photolithography and chemical mechanical polishing to achieve precise dimensions and material deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard width conductive lines are used at via junctions, then manufacturing is simpler, but electron migration and void formation increase
Solution Approach 1:
The patent applies local quality by varying the width of conductive lines based on their specific location and function within the interconnect structure. Wider conductive lines are formed at via junctions where electron migration is a concern, while narrower lines are used in other areas. This localized variation in geometric properties optimizes electron migration resistance at critical locations without unnecessarily increasing device complexity throughout the entire structure.
2Reliability
If wider conductive lines are formed at via junctions, then void formation is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary action by forming a mandrel structure with predetermined geometry before depositing the conductive material. The mandrel serves as a pre-formed template that defines the desired width variations of the conductive lines, including wider sections at via junctions. This preliminary structuring simplifies the subsequent deposition process and ensures precise width control without requiring complex real-time manufacturing adjustments.
Solution Approach 2:
The mandrel acts as an intermediary element that mediates between the manufacturing process and the final conductive line structure. By using the mandrel as a temporary forming structure, the patent achieves precise width control for varying conductive line dimensions. The mandrel is later removed, having served its purpose of defining the geometric properties of the conductive lines during fabrication.
3Productivity
If conductive lines are placed closer together, then interconnect density increases, but leakage current risk increases
Solution Approach 1:
The patent addresses leakage current concerns by transitioning from a two-dimensional spacing problem to a three-dimensional solution. Air gaps or voids are introduced as vertical separations between conductive lines, allowing lines to be placed closer together in the planar direction while maintaining electrical isolation through the vertical air gap dimension. This dimensional approach increases interconnect density without proportionally increasing leakage current risk.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces electron migration and void formation, maintaining minimum distances between conductive lines to prevent leakage current and dielectric breakdown, while allowing for efficient interconnect formation in semiconductor devices.
Implementation Method 1
Excess copper on the surface of the dielectric layer is then removed by a chemical mechanical polish (CMP).
Data Source
AI summary
An interconnect and a method of forming an interconnect for a semiconductor device is provided. Conductive lines having different widths are formed. Wider conductive lines are used where the design includes an overlying via, and narrower lines are used in which an overlying via is not included. An overlying dielectric layer is formed and trenches and vias are formed extending through the overlying dielectric layer to the wider conductive lines. Voids or air gaps may be formed adjacent select conductive lines, such as the narrower lines.