Semiconductor Interconnect Structures with Vertical Through-Holes

The patent transitions from two-dimensional planar interconnect structures to three-dimensional vertical interconnect structures. Through-holes extend vertically through multiple semiconductor layers, allowing electrical connections to be established in the vertical dimension rather than requiring large lateral cross-sections. This enables adequate contact area to be achieved through vertical extension rather than horizontal expansion, thereby reducing package size while maintaining electrical connection quality

The patent implements nested interconnect structures where conductive plugs are formed within through-holes that pass through multiple semiconductor layers. The conductive material is nested within the through-hole structure, and multiple such nested structures are arranged vertically to connect different layers. This nesting approach maximizes the use of vertical space for electrical connections without increasing lateral package dimensions

By moving interconnect structures into the vertical dimension through through-holes that penetrate multiple layers, the patent frees up lateral space for additional memory cells. The vertical orientation of interconnects allows memory arrays to be packed more densely in the planar direction without compromising electrical connection quality, thereby increasing overall memory density

The patent segments the interconnect structure into discrete through-holes distributed across the semiconductor substrate. Rather than requiring large continuous conductive regions, the electrical connections are segmented into multiple smaller through-holes that can be strategically placed. This segmentation allows maximum utilization of lateral space for memory cells while maintaining adequate electrical connections through the vertically distributed through-hole array

The patent compensates for reduced transverse cross-sectional dimensions by extending the interconnect structure in the vertical dimension. Through-holes provide extended contact paths through multiple semiconductor layers, increasing the effective contact area vertically without requiring larger lateral dimensions. This vertical extension maintains adequate electrical connection quality while enabling smaller package size

The patent changes the geometric parameters of the interconnect structure from lateral expansion to vertical extension. By modifying the orientation and dimensional distribution of the conductive paths, the effective contact area is increased through vertical length rather than horizontal width. This parameter change allows simultaneous reduction of package size and maintenance of low contact resistance