Semiconductor Interconnect Structure Without CMP Polishing
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Solution Overview
Problem
The chemical-mechanical polishing (CMP) process in semiconductor manufacturing is time-consuming and costly, and poses reliability issues, necessitating a more cost-effective and resource-saving method for forming interconnects and conductive lines.
Innovation Solution
A modified Damascene method that reduces the use of CMP processes by employing lift-off processes to form interconnects and conductive lines, using multiple lift-off processes to achieve results similar to traditional Damascene methods while minimizing the need for CMP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional Damascene process with CMP is used, then interconnects can be formed with good surface flatness, but the manufacturing time increases and costs increase
Solution Approach 1:
The patent extracts and removes the CMP process from the traditional Damascene flow, replacing it with a lift-off process. The insulating layers are selectively removed to expose conductive lines, and excess conductive material is lifted off using a sacrificial layer, eliminating the need for CMP while achieving the desired interconnect structure.
Solution Approach 2:
Instead of using CMP to achieve flat surfaces by removing material, the patent inverts the approach by using a lift-off process where excess material is removed after deposition. The sacrificial layer is removed first, causing the overhanging conductive material to lift off automatically, achieving the desired geometry without mechanical polishing.
2Manufacturing precision
If traditional Damascene process with CMP is used, then interconnects can be formed with good surface flatness, but the manufacturing cost increases
Solution Approach 1:
The patent extracts and removes the CMP process from the traditional Damascene flow, replacing it with a lift-off process. The insulating layers are selectively removed to expose conductive lines, and excess conductive material is lifted off using a sacrificial layer, eliminating the need for CMP while achieving the desired interconnect structure.
Solution Approach 2:
The patent introduces a sacrificial layer (e.g., silicon nitride or silicon oxide) that is intentionally deposited and then completely removed to enable the lift-off process. This disposable layer facilitates the removal of excess conductive material without requiring expensive CMP equipment or consumables, reducing overall manufacturing costs.
3Manufacturing precision
If CMP process is used extensively, then surface flatness is improved, but reliability problems occur
Solution Approach 1:
The patent extracts and removes the CMP process from the traditional Damascene flow, replacing it with a lift-off process. The insulating layers are selectively removed to expose conductive lines, and excess conductive material is lifted off using a sacrificial layer, eliminating the need for CMP while achieving the desired interconnect structure.
Solution Approach 2:
Instead of using CMP to achieve flat surfaces by removing material, the patent inverts the approach by using a lift-off process where excess material is removed after deposition. The sacrificial layer is removed first, causing the overhanging conductive material to lift off automatically, achieving the desired geometry without mechanical polishing.
Data Source
AI summary
The present application discloses a semiconductor structure and a method of manufacturing a semiconductor structure. The semiconductor structure includes a conductive line of an Nth metal layer, a first insulating layer, a dielectric layer, a second insulating layer, an interconnect base, and an interconnect body. The first insulating layer is on the conductive line and free from covering a portion of the conductive line. The dielectric layer is on the first insulating layer and free from covering the portion of the conductive line. The second insulating layer is on the dielectric layer and free from covering the portion of the conductive line. The interconnect base is laterally surrounded by the dielectric layer, the first insulating layer, and the second insulating layer. A top surface of the interconnect base and a top surface of the second insulating layer are coplanar.