Semiconductor Interconnection Layout Density Control
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Solution Overview
Problem
The existing techniques for planarizing interlayer insulating films in semiconductor devices, such as CMP, often result in 'dishing' due to variations in interconnection density, leading to unreliable semiconductor devices with deteriorated electrical characteristics and increased interconnect capacitance, especially when dummy interconnections are formed to suppress dishing.
Innovation Solution
A method of designing semiconductor devices by dividing the layout region into a matrix of unit regions and balancing the occupation ratio of high-density regions to less than 50%, thereby preventing the formation of dummy interconnections and ensuring precise end-point detection in dry etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy interconnections are formed to suppress dishing of the interlayer insulating film, then dishing is reduced, but interconnect capacitance increases and manufacturing complexity increases
Solution Approach 1:
The invention changes the design parameter of interconnection density distribution by controlling the occupation ratio of high-density regions to be less than 50%. This parameter change prevents dishing without requiring dummy interconnections, thereby avoiding the increase in interconnect capacitance and maintaining electrical characteristics.
Solution Approach 2:
The invention extracts and removes the unnecessary dummy interconnections from the design. By ensuring the occupation ratio of high-density regions is less than 50%, the patent eliminates the need for dummy interconnections while still achieving uniform film thickness, thus avoiding the harmful effects of increased capacitance and complexity.
2Manufacturing precision
If dummy interconnections are formed to suppress dishing, then film flatness improves, but device complexity increases
Solution Approach 1:
The invention extracts and removes dummy interconnections from the design by controlling the occupation ratio of high-density regions to be less than 50%. This simplifies the interconnection pattern while achieving uniform film thickness without the need for additional dummy structures.
Solution Approach 2:
By changing the design parameter of interconnection density distribution (occupation ratio < 50%), the patent achieves film flatness without requiring complex dummy interconnection patterns, thereby reducing device complexity.
3Productivity
If high interconnection density region occupies large area, then circuit functionality is enhanced, but dishing of interlayer insulating film occurs
Solution Approach 1:
The invention sets a specific parameter threshold (occupation ratio of high-density regions < 50%) to balance circuit integration density with film flatness. This parameter control allows sufficient circuit functionality while preventing dishing during the CMP process.
Data Source
AI summary
A method of designing a semiconductor device includes: (A) dividing a layout region of a semiconductor chip into matrix by a unit region; and (B) determining an interconnection layout such that an occupation ratio of a high-density region to the layout region is less than 50%. Here, the high-density region is a set of the unit regions in each of which interconnection density is higher than a predetermined reference value.