Semiconductor Interconnection Layout for Exposure Margin Optimization
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Solution Overview
Problem
In semiconductor storage devices, the peripheral region often faces challenges with exposure margin reduction due to optimized exposure conditions for the memory cell region, leading to difficulties in forming interconnections with design rules larger than the minimum value, which can result in decreased throughput and increased costs when separate reticles are used for different regions.
Innovation Solution
The solution involves forming interconnections in the peripheral region in the same direction as those in the memory cell region, using a connection member in a different layer to electrically connect interconnections, thereby matching the direction of interconnections and preventing exposure margin reduction, even when exposure conditions are optimized for the memory cell region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If exposure conditions are optimized for the memory cell region with minimum design rule, then the resolution and integration degree are improved, but the exposure margin is reduced for the peripheral region with larger design rules
Solution Approach 1:
The semiconductor device is divided into a memory cell region and a peripheral region, with each region having its own specific interconnection layout and design rules. The memory cell region uses minimum design rule F for high integration, while the peripheral region uses larger design rules for reliable interconnection formation, allowing each region to be optimized independently without compromising the other
Solution Approach 2:
Different regions of the semiconductor device are assigned different design rule requirements: the memory cell region operates at minimum design rule F to maximize integration density, while the peripheral region uses larger design rules to ensure adequate exposure margin and manufacturing reliability. This local differentiation allows simultaneous optimization of both regions
2Manufacturing precision
If separate reticles are used for memory cell region and peripheral region to accommodate different design rules, then the manufacturing precision for each region is improved, but the device complexity and production cost increase
Solution Approach 1:
The patent combines the memory cell region and peripheral region into a single reticle design that can be exposed simultaneously. By carefully designing the interconnection layouts and using connection members in the peripheral region, both regions with different design rule requirements can be manufactured using one reticle, thereby reducing complexity and cost while maintaining manufacturing precision
3Manufacturing precision
If separate reticles are used for different regions, then the manufacturing precision for each region is improved, but the productivity decreases due to increased processing steps
Solution Approach 1:
The patent enables simultaneous exposure of both memory cell and peripheral regions using a single reticle, eliminating the need for separate exposure steps. This merging of regions into one exposure process maintains manufacturing precision for region-specific design rules while significantly improving productivity by reducing the total number of processing steps and increasing throughput
Data Source
AI summary
A lack of exposure margin is avoided in a region, where an interconnection is required in a direction different from that of an interconnection of a region where an exposure condition is optimized. A semiconductor device According to an aspect of the invention includes a semiconductor substrate 201; an interlayer insulating film 202 that is formed on the semiconductor substrate 201; a plurality of first interconnections 1, 1, . . . that are formed in a first region on the interlayer insulating film 202 while complying with a first design rule, the first interconnections running along a specific direction; a plurality of second interconnections 2, 2, . . . that are formed in a second region on the interlayer insulating film 202 while complying with a second design rule identical to the first design rule, the second interconnections running along the same direction with that of the first interconnections 1, 1, . . . ; and a connection member 3 that is formed in the interlayer insulating film 202, the connection member forming a desired interconnection pattern by electrically connecting at least the two second interconnections 2 and 2 that should become an identical potential.