Semiconductor Interconnection Liner RuCo Alloy Design
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of MOSFETs deteriorate due to high integration, leading to challenges in achieving excellent performance.
Innovation Solution
A semiconductor device design incorporating a substrate with transistors, interlayer insulating layers, and interconnection lines, where the first interconnection line includes a ruthenium cobalt (RuCo) compound liner and the second interconnection line includes cobalt (Co) liner, with specific height ratios and recess profiles to enhance electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET size is reduced for high integration, then device density increases, but operating characteristics deteriorate
Solution Approach 1:
The interconnection line is segmented into multiple functional layers: barrier pattern, liner layer, and conductive pattern. This segmentation allows each layer to perform its specific function optimally, contributing to overall device performance despite scaling
Solution Approach 2:
The liner layer uses a composite structure of RuCo alloy (first liner) and Co (second liner) with different properties. The RuCo layer provides adhesion and diffusion barrier, while the Co layer provides electrical conductivity, creating a composite material system that optimizes both electrical characteristics and structural integrity
2Ease of manufacture
If conventional interconnection line structure is used, then manufacturing is simpler, but resistance is higher and delamination occurs
Solution Approach 1:
The thickness ratio of the conductive pattern to the liner layer is controlled within 10:1 to 20:1, optimizing electrical resistance. The liner layer thickness is precisely controlled at 1-5 nm to provide adequate adhesion and diffusion barrier without excessive resistance
Solution Approach 2:
The multi-layer composite structure (barrier + RuCo liner + Co liner + conductive pattern) provides both mechanical adhesion prevention against delamination and electrical resistance reduction, while remaining compatible with existing manufacturing processes
3Ease of manufacture
If single material liner is used, then manufacturing is easier, but adhesion and diffusion barrier are insufficient
Solution Approach 1:
The dual-layer liner structure uses RuCo alloy as the first liner for adhesion to the barrier pattern and diffusion barrier, while Co serves as the second liner for electrical conductivity and adhesion to the conductive pattern. This composite approach addresses multiple functional requirements simultaneously
Solution Approach 2:
Different portions of the liner structure have different material compositions optimized for their specific functions: RuCo at the barrier interface for adhesion and diffusion control, Co at the conductive interface for electrical performance, creating local quality variations throughout the interconnection structure
Data Source
AI summary
Provided is a semiconductor device including a substrate including an active region, transistors on the substrate, a first interlayer insulating layer and a second interlayer insulating layer on the transistors, a first interconnection line in an upper portion of the first interlayer insulating layer, and a second interconnection line in the second interlayer insulating layer, wherein the first interconnection line includes a first barrier pattern, a first liner, and a first conductive pattern, wherein the second interconnection line includes a second barrier pattern, a second liner, and a second conductive pattern, wherein first height between an uppermost portion of a top surface of the first conductive pattern and a lowermost portion of a top surface of the first liner is greater than a second height between an uppermost portion of a top surface of the second conductive pattern and a lowermost portion of a top surface of the second liner.