Semiconductor Interconnection Patterns with Protruding Contact Pads
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Solution Overview
Problem
Current methods for forming fine patterns in semiconductor devices face challenges in achieving sufficient contact area between interconnection lines and contact plugs, leading to increased electric resistance due to limitations in photolithography resolution and contact area, particularly in double pattern technology processes.
Innovation Solution
A method involving the formation of a conductive layer with protruding portions on a substrate, where mask patterns are used to etch the layer, creating line patterns and contact pads that are connected as a single body, with the contact pads being wider than the line patterns to enhance contact area and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double pattern technology DPT process is used to form interconnection lines, then finer patterns can be achieved, but contact area between contact plugs and interconnection lines becomes insufficient
Solution Approach 1:
The conductive layer is segmented into a plate portion and multiple protruding portions, where the protruding portions extend in a first direction to provide enhanced contact area. This segmentation allows the interconnection structure to maintain fine pitch while ensuring sufficient contact area between contact plugs and interconnection lines.
Solution Approach 2:
The conductive layer is designed with three-dimensional structure featuring protruding portions that extend laterally. This dimensional transformation from a simple planar line to a structured form with extended surfaces increases the contact interface area without increasing the overall footprint, thereby resolving the contradiction between fine patterning and sufficient contact area.
2Productivity
If pattern pitch is reduced to increase devices per area, then integration density improves, but photolithography resolution becomes insufficient
Solution Approach 1:
The conductive layer is divided into a plate portion and multiple protruding portions spaced apart in a second direction. This segmentation enables the formation of multiple functional regions within a compact area, achieving high integration density while maintaining manufacturable feature sizes through conventional photolithography processes.
Solution Approach 2:
The plate portion and protruding portions are merged into a single continuous conductive layer structure, forming an integrated interconnection pattern that combines the benefits of compact layout (for high density) with extended contact surfaces (for reliable electrical connection).
3Reliability
If contact area is increased to reduce electric resistance, then electrical performance improves, but interconnection line width must be increased
Solution Approach 1:
Instead of increasing line width in the planar dimension, the invention extends the conductive layer vertically and laterally to create protruding portions. This dimensional transformation increases the contact surface area without increasing the effective line width, thereby reducing electrical resistance while maintaining compact interconnection geometry.
Solution Approach 2:
The conductive layer exhibits different local geometries: the plate portion provides the main interconnection path with controlled width, while the protruding portions provide extended contact surfaces. This local quality variation allows the structure to optimize both electrical connection (at the protruding portions) and signal transmission (through the plate portion) independently.
Data Source
AI summary
A method of forming fine patterns for a semiconductor device includes providing a substrate with a first region and a second region, forming a conductive layer on the substrate, the conductive layer including a plate portion covering the first region and first protruding portions extending from the plate portion in a first direction and covering a portion of the second region, forming first mask patterns on the conductive layer, the first mask patterns extending in the first direction and being spaced apart from each other in a second direction crossing the first direction, forming a second mask pattern on the second region to cover the first protruding portions, and patterning the conductive layer using the first and second mask patterns as an etch mask to form conductive patterns. In plan view, each of the first protruding portions is overlapped with a corresponding one of the first mask patterns.