Semiconductor Interconnection Segmentation for Cavity Airtightness
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Solution Overview
Problem
Conventional semiconductor devices with movable elements in sealed cavities face challenges in ensuring airtightness while reducing electric resistance, as large irregularities at the joint frame's upper surface hinder close joining of the cap and joint frame, and reducing interconnection thickness to mitigate this issue complicates achieving both airtightness and low electric resistance.
Innovation Solution
The semiconductor device design incorporates a substrate with a groove, featuring a first interconnection along the groove's bottom with a smaller thickness and a second interconnection with a larger thickness, electrically connected to the element, and a member surrounding the element and interconnection, allowing for a cap to form a cavity. This configuration uses isotropic etching to gently step the insulating film edges, reducing surface irregularities and enabling close joining of the cap and member for improved airtightness and reduced electric resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the interconnection is reduced to reduce surface irregularities, then the airtightness of the cavity is improved, but the electric resistance of the interconnection increases
Solution Approach 1:
The interconnection is divided into two segments with different thicknesses: a first interconnection layer with smaller thickness formed along the groove bottom, and a second interconnection layer with larger thickness formed on the substrate. This segmentation allows the lower segment to minimize surface irregularities for airtightness while the upper segment provides low electric resistance, resolving the contradiction between these two requirements.
2Manufacturing precision
If the thickness of the interconnection is increased to reduce electric resistance, then the electric resistance of the interconnection is reduced, but the surface irregularities at the joint frame increase
Solution Approach 1:
Different regions of the interconnection structure are assigned different thickness qualities: the region adjacent to the groove (first interconnection) has smaller thickness to minimize surface irregularities, while the region on the substrate surface (second interconnection) has larger thickness to reduce electric resistance. This local differentiation of quality allows each region to optimize for its specific function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively ensures airtightness of the cavity and reduces the electric resistance of the interconnection by minimizing surface irregularities and allowing for close joining of the cap and member, while also enabling collective patterning of interconnections to reduce irregularities caused by overlapping deviations.
Implementation Method 1
The insulating film not covered with the first mask layer is removed by isotropic etching
Data Source
AI summary
A first interconnection is formed along a groove of a substrate and on a bottom surface of the groove, and has a first thickness. A second interconnection is electrically connected to the first interconnection and has a second thickness larger than the first thickness. An acceleration sensing unit is electrically connected to the second interconnection. A sealing unit has a portion opposed to the substrate with the first interconnection therebetween, and surrounds the second interconnection and the acceleration sensing unit on the substrate. A cap is arranged on the sealing unit to form a cavity on a region of the substrate surrounded by the sealing unit. Thereby, airtightness of the cavity can be ensured and also an electric resistance of the interconnection connected to the acceleration sensing unit can be reduced.