Semiconductor Package Interconnection Segmentation for Yield

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Solution Overview

Problem

Semiconductor device packages with multi-layered redistribution layers (RDLs) face yield decreases as the number of layers increases, leading to low yield and inefficient signal transmission due to the need to connect both high-density and low-density input/output (I/O) terminals.

Innovation Solution

The use of separate low-density and high-density interconnection structures, each formed by distinct processes, to individually manage low-density and high-density I/O regions between semiconductor dies, reducing the number of layers and shortening signal transmission paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multi-layered redistribution layers (RDLs) are used to connect both high-density and low-density I/O terminals, then electrical functionality between semiconductor dies is achieved, but the yield decreases as the number of layers increases

Engineering Contradiction:
Improveelectrical functionalityVSAvoidyield
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent divides the interconnection system into separate high-density interconnection structures and low-density interconnection structures. Each structure handles its respective density independently, eliminating the need for multi-layered RDLs to accommodate both densities simultaneously. This segmentation maintains electrical functionality while reducing the number of layers required, thereby improving yield.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If multi-layered RDLs are used to redistribute signals from both high-density and low-density I/O terminals, then signal redistribution is achieved, but the number of layers increases leading to low yield

Engineering Contradiction:
Improvesignal redistributionVSAvoidnumber of layers
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The interconnection system is segmented into distinct high-density and low-density pathways. Each pathway is optimized for its specific density requirements, allowing signal redistribution to occur in separate layers rather than requiring multiple layers to accommodate both densities. This reduces the overall layer count while maintaining full signal redistribution capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different interconnection structures are used in different regions of the semiconductor package - high-density structures in regions requiring high terminal density and low-density structures in other regions. This local optimization allows each region to use the most appropriate interconnection type, reducing the need for complex multi-layered RDL designs.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If multi-layered RDLs are used to connect high-density and low-density I/O terminals, then both terminal types are connected, but signal transmission efficiency decreases due to increased layer count

Engineering Contradiction:
Improveterminal connectionVSAvoidsignal transmission efficiency
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

By separating high-density and low-density I/O terminal connections into distinct interconnection structures, the patent reduces the number of layers signals must traverse. High-density signals travel through high-density interconnection structures and low-density signals through low-density structures, eliminating the need to navigate through multiple RDL layers and improving signal transmission efficiency.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11600567B2Semiconductor device package and method for manufacturing the same
Publication Date: 2023.03.07 ADVANCED SEMICON ENG INC
  • US11600567B2 patent drawing
  • US11600567B2 patent drawing
  • US11600567B2 patent drawing

AI summary

A semiconductor device package includes a first circuit layer, a second circuit layer, a first semiconductor die and a second semiconductor die. The first circuit layer includes a first surface and a second surface opposite to the first surface. The second circuit layer is disposed on the first surface of the first circuit layer. The first semiconductor die is disposed on the first circuit layer and the second circuit layer, and electrically connected to the first circuit layer and the second circuit layer. The second semiconductor die is disposed on the second circuit layer, and electrically connected to the second circuit layer.